Determinou o
endereço de A
A
06 - add r1,r2,r3
05 - xor r11,r12,r13
Next SEQ PC
Next SEQ PC
Adder
4
MUX
MEM/WB
Data
Memory
EX/MEM
Instr. 05 – xor r11,r12,r13
ALU
Instr. 04 – sub r8,r9,r10
Imm
MUX MUX
Instr. 03 – or r5,r6,r7
ID/EX
Instr. 02 – and r2,r3,r4
Reg File
IF/ID
Memory
Address
Instr. 01 – add r1,r2,r3
02 - and r2,r3,r4
Zero?
RS1
RS2
03 - or r5,r6,r7
MUX
Next PC
04 - sub r8,r9,r10
WB Data
Ciclo 6
Sign
Extend
RD
RD
RD
Instr. 06 – add r1,r2,r3
Instr. 07 – and r2,r3,r4
Instr. 08 – or r5,r6,r7
Instr. 09 – sub r8,r9,r10
Instr. 10 – xor r11,r12,r13
CS252-s06, Lec 02-intro
1
Determinou o
endereço de A
A
07 - and r2,r3,r4
06 - add r1,r2,r3
Next SEQ PC
Next SEQ PC
Adder
4
MUX
MEM/WB
Data
Memory
EX/MEM
Instr. 05 – xor r11,r12,r13
ALU
Instr. 04 – sub r8,r9,r10
Imm
MUX MUX
Instr. 03 – or r5,r6,r7
ID/EX
Instr. 02 – and r2,r3,r4
Reg File
IF/ID
Memory
Address
Instr. 01 – add r1,r2,r3
03 - or r5,r6,r7
Zero?
RS1
RS2
04 - sub r8,r9,r10
MUX
Next PC
05 - xor r11,r12,r13
WB Data
Ciclo 7
Sign
Extend
RD
RD
RD
Instr. 06 – add r1,r2,r3
Instr. 07 – and r2,r3,r4
Instr. 08 – or r5,r6,r7
Instr. 09 – sub r8,r9,r10
Instr. 10 – xor r11,r12,r13
CS252-s06, Lec 02-intro
2
Determinou o
endereço de A
A
08 - or r5,r6,r7
07 - and r2,r3,r4
Next SEQ PC
Next SEQ PC
Adder
4
Zero?
RS1
MUX
MEM/WB
Data
Memory
Instr. 05 – xor r11,r12,r13
EX/MEM
Instr. 04 – sub r8,r9,r10
Imm
ALU
Instr. 03 – or r5,r6,r7
MUX MUX
Instr. 02 – and r2,r3,r4
ID/EX
Instr. 01 – add r1,r2,r3
Reg File
IF/ID
Memory
Address
RS2
05 - xor r11,r12,r13 04 - sub r8,r9,r10
MUX
Next PC
06 - add r1,r2,r3
WB Data
Ciclo 8
Sign
Extend
RD
RD
RD
Instr. 06 – add r1,r2,r3
Instr. 07 – and r2,r3,r4
Instr. 08 – or r5,r6,r7
Instr. 09 – sub r8,r9,r10
Instr. 10 – xor r11,r12,r13
CS252-s06, Lec 02-intro
3
Determinou o
endereço de A
A
08 - or r5,r6,r7
09 - sub r8,r9,r10
Next SEQ PC
Next SEQ PC
Adder
4
Zero?
RS1
MUX
MEM/WB
Data
Memory
Instr. 05 – xor r11,r12,r13
EX/MEM
Instr. 04 – sub r8,r9,r10
Imm
ALU
Instr. 03 – or r5,r6,r7
MUX MUX
Instr. 02 – and r2,r3,r4
ID/EX
Instr. 01 – add r1,r2,r3
Reg File
IF/ID
Memory
Address
RS2
06 - add r1,r2,r3 05 - xor r11,r12,r13
MUX
Next PC
07 - and r2,r3,r4
WB Data
Ciclo 9
Sign
Extend
RD
RD
RD
Instr. 06 – add r1,r2,r3
Instr. 07 – and r2,r3,r4
Instr. 08 – or r5,r6,r7
Instr. 09 – sub r8,r9,r10
Instr. 10 – xor r11,r12,r13
CS252-s06, Lec 02-intro
4
Determinou o
endereço de A
A
09 - sub r8,r9,r10
10 - xor r11,r12,r13
Next SEQ PC
Next SEQ PC
Adder
4
MUX
MEM/WB
Data
Memory
EX/MEM
Instr. 05 – xor r11,r12,r13
ALU
Instr. 04 – sub r8,r9,r10
Imm
MUX MUX
Instr. 03 – or r5,r6,r7
ID/EX
Instr. 02 – and r2,r3,r4
Reg File
IF/ID
Memory
Address
Instr. 01 – add r1,r2,r3
06 - add r1,r2,r3
Zero?
RS1
RS2
07 - and r2,r3,r4
MUX
Next PC
08 - or r5,r6,r7
WB Data
Ciclo 10
Sign
Extend
RD
RD
RD
Instr. 06 – add r1,r2,r3
Instr. 07 – and r2,r3,r4
Instr. 08 – or r5,r6,r7
Instr. 09 – sub r8,r9,r10
Instr. 10 – xor r11,r12,r13
CS252-s06, Lec 02-intro
5
A
Determinou o
endereço de A
Com dependência de dados
06 - add r1,r2,r3
05 - xor r11,r12,r13
Next SEQ PC
Next SEQ PC
Adder
4
MUX
MEM/WB
Data
Memory
EX/MEM
Instr. 05 – xor r11,r12,r13
ALU
Instr. 04 – sub r8,r9,r10
Imm
MUX MUX
Instr. 03 – or r5,r6,r7
ID/EX
Instr. 02 – and r2,r3,r4
Reg File
IF/ID
Memory
Address
Instr. 01 – add r1,r2,r3
02 - and r2,r3,r4
Zero?
RS1
RS2
03 - or r5,r6,r7
MUX
Next PC
04 - sub r8,r9,r10
WB Data
Ciclo 6
Sign
Extend
RD
RD
RD
Instr. 06 – add r1,r2,r3
Instr. 07 – and r2,r1,r4
Instr. 08 – or r5,r6,r7
Instr. 09 – sub r8,r9,r10
Instr. 10 – xor r11,r12,r13
CS252-s06, Lec 02-intro
6
Determinou o
endereço de A
A
07 - and r2,r1,r4
06 - add r1,r2,r3
Next SEQ PC
Next SEQ PC
Adder
4
MUX
MEM/WB
Data
Memory
EX/MEM
Instr. 05 – xor r11,r12,r13
ALU
Instr. 04 – sub r8,r9,r10
Imm
MUX MUX
Instr. 03 – or r5,r6,r7
ID/EX
Instr. 02 – and r2,r3,r4
Reg File
IF/ID
Memory
Address
Instr. 01 – add r1,r2,r3
03 - or r5,r6,r7
Zero?
RS1
RS2
04 - sub r8,r9,r10
MUX
Next PC
05 - xor r11,r12,r13
WB Data
Ciclo 7
Sign
Extend
RD
RD
RD
Instr. 06 – add r1,r2,r3
Instr. 07 – and r2,r1,r4
Instr. 08 – or r5,r6,r7
Instr. 09 – sub r8,r9,r10
Instr. 10 – xor r11,r12,r13
CS252-s06, Lec 02-intro
7
Determinou o
endereço de A
A
08 - or r5,r6,r7
07 - and r2,r1,r4
Next SEQ PC
Next SEQ PC
Adder
4
Zero?
RS1
MUX
MEM/WB
Data
Memory
Instr. 05 – xor r11,r12,r13
EX/MEM
Instr. 04 – sub r8,r9,r10
Imm
ALU
Instr. 03 – or r5,r6,r7
MUX MUX
Instr. 02 – and r2,r3,r4
ID/EX
Instr. 01 – add r1,r2,r3
Reg File
IF/ID
Memory
Address
RS2
05 - xor r11,r12,r13 04 - sub r8,r9,r10
MUX
Next PC
06 - add r1,r2,r3
WB Data
Ciclo 8
Sign
Extend
RD
RD
RD
Instr. 06 – add r1,r2,r3
Instr. 07 – and r2,r1,r4
Instr. 08 – or r5,r6,r7
Instr. 09 – sub r8,r9,r10
Instr. 10 – xor r11,r12,r13
CS252-s06, Lec 02-intro
8
Determinou o
endereço de A
A
08 - or r5,r6,r7
07 - and r2,r1,r4
Next SEQ PC
Next SEQ PC
Adder
4
Zero?
RS1
MUX
MEM/WB
Data
Memory
Instr. 05 – xor r11,r12,r13
EX/MEM
Instr. 04 – sub r8,r9,r10
Imm
ALU
Instr. 03 – or r5,r6,r7
MUX MUX
Instr. 02 – and r2,r3,r4
ID/EX
Instr. 01 – add r1,r2,r3
Reg File
IF/ID
Memory
Address
RS2
06 - add r1,r2,r3 05 - xor r11,r12,r13
MUX
Next PC
bolha
WB Data
Ciclo 9
Sign
Extend
RD
RD
RD
Instr. 06 – add r1,r2,r3
Instr. 07 – and r2,r1,r4
Instr. 08 – or r5,r6,r7
Instr. 09 – sub r8,r9,r10
Instr. 10 – xor r11,r12,r13
CS252-s06, Lec 02-intro
9
Determinou o
endereço de A
A
08 - or r5,r6,r7
07 - and r2,r1,r4
Next SEQ PC
Next SEQ PC
Adder
4
MUX
MEM/WB
Data
Memory
EX/MEM
Instr. 05 – xor r11,r12,r13
ALU
Instr. 04 – sub r8,r9,r10
Imm
MUX MUX
Instr. 03 – or r5,r6,r7
ID/EX
Instr. 02 – and r2,r3,r4
Reg File
IF/ID
Memory
Address
Instr. 01 – add r1,r2,r3
06 - add r1,r2,r3
Zero?
RS1
RS2
bolha
MUX
Next PC
bolha
WB Data
Ciclo 10
Sign
Extend
RD
RD
RD
Instr. 06 – add r1,r2,r3
Instr. 07 – and r2,r1,r4
Instr. 08 – or r5,r6,r7
Instr. 09 – sub r8,r9,r10
Instr. 10 – xor r11,r12,r13
CS252-s06, Lec 02-intro
10
Determinou o
endereço de A
A
08 - or r5,r6,r7
07 - and r2,r1,r4
Next SEQ PC
Next SEQ PC
Adder
4
MUX
MEM/WB
Data
Memory
EX/MEM
Instr. 05 – xor r11,r12,r13
ALU
Instr. 04 – sub r8,r9,r10
Imm
MUX MUX
Instr. 03 – or r5,r6,r7
ID/EX
Instr. 02 – and r2,r3,r4
Reg File
IF/ID
Memory
Address
Instr. 01 – add r1,r2,r3
bolha
Zero?
RS1
RS2
bolha
MUX
Next PC
bolha
WB Data
Ciclo 11
Sign
Extend
RD
RD
RD
Instr. 06 – add r1,r2,r3
Instr. 07 – and r2,r1,r4
Instr. 08 – or r5,r6,r7
Instr. 09 – sub r8,r9,r10
Instr. 10 – xor r11,r12,r13
CS252-s06, Lec 02-intro
11
Determinou o
endereço de A
A
08 - or r5,r6,r7
09 - sub r8,r9,r10
Next SEQ PC
Next SEQ PC
Adder
4
MUX
MEM/WB
Data
Memory
EX/MEM
Instr. 05 – xor r11,r12,r13
ALU
Instr. 04 – sub r8,r9,r10
Imm
MUX MUX
Instr. 03 – or r5,r6,r7
ID/EX
Instr. 02 – and r2,r3,r4
Reg File
IF/ID
Memory
Address
Instr. 01 – add r1,r2,r3
bolha
Zero?
RS1
RS2
bolha
MUX
Next PC
07 - and r2,r1,r4
WB Data
Ciclo 12
Sign
Extend
RD
RD
RD
Instr. 06 – add r1,r2,r3
Instr. 07 – and r2,r3,r4
Instr. 08 – or r5,r6,r7
Instr. 09 – sub r8,r9,r10
Instr. 10 – xor r11,r12,r13
CS252-s06, Lec 02-intro
12
Determinou o
endereço de A
A
09 - sub r8,r9,r10
10 - xor r11,r12,r13
Next SEQ PC
Next SEQ PC
Adder
4
MUX
MEM/WB
Data
Memory
EX/MEM
Instr. 05 – xor r11,r12,r13
ALU
Instr. 04 – sub r8,r9,r10
Imm
MUX MUX
Instr. 03 – or r5,r6,r7
ID/EX
Instr. 02 – and r2,r3,r4
Reg File
IF/ID
Memory
Address
Instr. 01 – add r1,r2,r3
bolha
Zero?
RS1
RS2
07 - and r2,r3,r4
MUX
Next PC
08 - or r5,r6,r7
WB Data
Ciclo 13
Sign
Extend
RD
RD
RD
Instr. 06 – add r1,r2,r3
Instr. 07 – and r2,r3,r4
Instr. 08 – or r5,r6,r7
Instr. 09 – sub r8,r9,r10
Instr. 10 – xor r11,r12,r13
CS252-s06, Lec 02-intro
13
Forwarding
NextPC
mux
MEM/WR
EX/MEM
ALU
mux
ID/EX
Registers
Data
Memory
mux
Immediate
CS252-s06, Lec 02-intro
14
A
Determinou o
endereço de A
Com forwarding
06 - add r1,r2,r3
05 - xor r11,r12,r13
Next SEQ PC
Next SEQ PC
Adder
4
MUX
MEM/WB
Data
Memory
EX/MEM
Instr. 05 – xor r11,r12,r13
ALU
Instr. 04 – sub r8,r9,r10
Imm
MUX MUX
Instr. 03 – or r5,r6,r7
ID/EX
Instr. 02 – and r2,r3,r4
Reg File
IF/ID
Memory
Address
Instr. 01 – add r1,r2,r3
02 - and r2,r3,r4
Zero?
RS1
RS2
03 - or r5,r6,r7
MUX
Next PC
04 - sub r8,r9,r10
WB Data
Ciclo 6
Sign
Extend
RD
RD
RD
Instr. 06 – add r1,r2,r3
Instr. 07 – and r2,r1,r4
Instr. 08 – or r5,r1,r7
Instr. 09 – sub r8,r1,r10
Instr. 10 – xor r11,r1,r13
CS252-s06, Lec 02-intro
15
Determinou o
endereço de A
A
07 - and r2,r1,r4
06 - add r1,r2,r3
Next SEQ PC
Next SEQ PC
Adder
4
MUX
MEM/WB
Data
Memory
EX/MEM
Instr. 05 – xor r11,r12,r13
ALU
Instr. 04 – sub r8,r9,r10
Imm
MUX MUX
Instr. 03 – or r5,r6,r7
ID/EX
Instr. 02 – and r2,r3,r4
Reg File
IF/ID
Memory
Address
Instr. 01 – add r1,r2,r3
03 - or r5,r6,r7
Zero?
RS1
RS2
04 - sub r8,r9,r10
MUX
Next PC
05 - xor r11,r12,r13
WB Data
Ciclo 7
Sign
Extend
RD
RD
RD
Instr. 06 – add r1,r2,r3
Instr. 07 – and r2,r1,r4
Instr. 08 – or r5,r1,r7
Instr. 09 – sub r8,r1,r10
Instr. 10 – xor r11,r1,r13
CS252-s06, Lec 02-intro
16
A
08 - or r5,r1,r7
Determinou o
endereço de A
07 - and r2,r1,r4
Next SEQ PC
Next SEQ PC
Adder
4
Zero?
RS1
MUX
MEM/WB
Data
Memory
Instr. 05 – xor r11,r12,r13
EX/MEM
Instr. 04 – sub r8,r9,r10
Imm
ALU
Instr. 03 – or r5,r6,r7
MUX MUX
Instr. 02 – and r2,r3,r4
ID/EX
Instr. 01 – add r1,r2,r3
Reg File
IF/ID
Memory
Address
RS2
05 - xor r11,r12,r13 04 - sub r8,r9,r10
MUX
Next PC
06 - add r1,r2,r3
WB Data
Ciclo 8
Vai ler o valor
errado no fim
do ciclo
Sign
Extend
RD
RD
RD
Instr. 06 – add r1,r2,r3
Instr. 07 – and r2,r1,r4
Instr. 08 – or r5,r1,r7
Instr. 09 – sub r8,r1,r10
Instr. 10 – xor r11,r1,r13
CS252-s06, Lec 02-intro
17
A
Usa o valor
correto via
forwarding
08 - or r5,r1,r7
09 - sub r8,r1,r10
Next SEQ PC
Next SEQ PC
Adder
4
Zero?
RS1
MUX
MEM/WB
Data
Memory
Instr. 05 – xor r11,r12,r13
EX/MEM
Instr. 04 – sub r8,r9,r10
Imm
ALU
Instr. 03 – or r5,r6,r7
MUX MUX
Instr. 02 – and r2,r3,r4
ID/EX
Instr. 01 – add r1,r2,r3
Reg File
IF/ID
Memory
Address
RS2
06 - add r1,r2,r3 05 - xor r11,r12,r13
MUX
Next PC
07 - and r2,r1,r4
Determinou o
endereço de A
WB Data
Ciclo 9
Vai ler o valor
errado no fim
do ciclo
Sign
Extend
RD
RD
RD
Instr. 06 – add r1,r2,r3
Instr. 07 – and r2,r1,r4
Instr. 08 – or r5,r1,r7
Instr. 09 – sub r8,r1,r10
Instr. 10 – xor r11,r1,r13
CS252-s06, Lec 02-intro
18
A
Usa o valor
correto via
forwarding
08 - or r5,r1,r7
09 - sub r8,r1,r10
10 - xor r11,r1,r13
Next SEQ PC
Next SEQ PC
Adder
4
MUX
MEM/WB
Data
Memory
EX/MEM
Instr. 05 – xor r11,r12,r13
ALU
Instr. 04 – sub r8,r9,r10
Imm
MUX MUX
Instr. 03 – or r5,r6,r7
ID/EX
Instr. 02 – and r2,r3,r4
Reg File
IF/ID
Memory
Address
Instr. 01 – add r1,r2,r3
06 - add r1,r2,r3
Zero?
RS1
RS2
07 - and r2,r1,r4
MUX
Next PC
Determinou o
endereço de A
WB Data
Ciclo 10
Vai ler o valor
certo no fim do
ciclo
Sign
Extend
RD
RD
RD
Instr. 06 – add r1,r2,r3
Instr. 07 – and r2,r1,r4
Instr. 08 – or r5,r1,r7
Instr. 09 – sub r8,r1,r10
Instr. 10 – xor r11,r1,r13
Registradores feitos
com FFs tipo D
acionados por nívelCS252-s06,
Lec 02-intro
19
A
08 - or r5,r6,r7
07 - and r2,r1,r4
06 - lw r1,0(r3)
Next SEQ PC
Next SEQ PC
Adder
Zero?
RS1
MUX
MEM/WB
Data
Memory
Instr. 05 – xor r11,r12,r13
EX/MEM
Instr. 04 – sub r8,r9,r10
Imm
ALU
Instr. 03 – or r5,r6,r7
MUX MUX
Instr. 02 – and r2,r3,r4
ID/EX
Instr. 01 – add r1,r2,r3
Reg File
IF/ID
Memory
Address
RS2
05 - xor r11,r12,r13 04 - sub r8,r9,r10
MUX
Next PC
4
Determinou o
endereço de A
Dependência verdadeira - LW
WB Data
Ciclo 8
Sign
Extend
RD
RD
RD
Instr. 06 – lw r1,0(r3)
Instr. 07 – and r2,r1,r4
Instr. 08 – or r5,r6,r7
Instr. 09 – sub r8,r9,r10
Instr. 10 – xor r11,r12,r13
CS252-s06, Lec 02-intro
20
Determinou o
endereço de A
A
08 - or r5,r6,r7
Next SEQ PC
Next SEQ PC
Adder
4
MUX
MEM/WB
Data
Memory
EX/MEM
Instr. 05 – xor r11,r12,r13
ALU
Instr. 04 – sub r8,r9,r10
Imm
MUX MUX
Instr. 03 – or r5,r6,r7
ID/EX
Instr. 02 – and r2,r3,r4
Reg File
IF/ID
Memory
Address
Instr. 01 – add r1,r2,r3
05 - xor r11,r12,r13
Zero?
RS1
RS2
06 - lw r1,0(r3)
bolha
MUX
Next PC
07 - and r2,r1,r4
WB Data
Ciclo 9
Sign
Extend
RD
RD
RD
Instr. 06 – lw r1,0(r3)
Instr. 07 – and r2,r1,r4
Instr. 08 – or r5,r6,r7
Instr. 09 – sub r8,r9,r10
Instr. 10 – xor r11,r12,r13
CS252-s06, Lec 02-intro
21
Determinou o
endereço de A
A
08 - or r5,r6,r7
09 - sub r8,r1,r10
Next SEQ PC
Next SEQ PC
Adder
4
Zero?
RS1
MUX
MEM/WB
Data
Memory
Instr. 05 – xor r11,r12,r13
EX/MEM
Instr. 04 – sub r8,r9,r10
Imm
ALU
Instr. 03 – or r5,r6,r7
MUX MUX
Instr. 02 – and r2,r3,r4
ID/EX
Instr. 01 – add r1,r2,r3
Reg File
IF/ID
Memory
Address
RS2
06 - lw r1,0(r3)
bolha
MUX
Next PC
07 - and r2,r1,r4
WB Data
Ciclo 10
Sign
Extend
RD
RD
RD
Instr. 06 – lw r1,0(r3)
Instr. 07 – and r2,r1,r4
Instr. 08 – or r5,r6,r7
Instr. 09 – sub r8,r9,r10
Instr. 10 – xor r11,r12,r13
CS252-s06, Lec 02-intro
22
A
Desvios condicionais – bolhas para trás
06 - beqz r1, i10
05 - xor r11,r12,r13
Next SEQ PC
Next SEQ PC
Adder
4
MUX
MEM/WB
Data
Memory
EX/MEM
Instr. 05 – xor r11,r12,r13
ALU
Instr. 04 – sub r8,r9,r10
Imm
MUX MUX
Instr. 03 – or r5,r6,r7
ID/EX
Instr. 02 – and r2,r3,r4
Reg File
IF/ID
Memory
Address
Instr. 01 – add r1,r2,r3
02 - and r2,r3,r4
Zero?
RS1
RS2
03 - or r5,r6,r7
MUX
Next PC
04 - sub r8,r9,r10
Determinou o
endereço de A
WB Data
Ciclo 6
Sign
Extend
RD
RD
RD
Instr. 06 – beqz r1, i10
Instr. 07 – and r2,r3,r4
Instr. 08 – or r5,r6,r7
Instr. 09 – sub r8,r9,r10
Instr. 10 – xor r11,r12,r13
CS252-s06, Lec 02-intro
23
Determinou o
endereço de A
A
07 - and r2,r3,r4
05 - xor r11,r12,r13
06 - beqz r1, i10
Next SEQ PC
Next SEQ PC
Adder
4
Zero?
RS1
MUX
MEM/WB
Data
Memory
Instr. 05 – xor r11,r12,r13
EX/MEM
Instr. 04 – sub r8,r9,r10
Imm
ALU
Instr. 03 – or r5,r6,r7
MUX MUX
Instr. 02 – and r2,r3,r4
ID/EX
Instr. 01 – add r1,r2,r3
Reg File
IF/ID
Memory
Address
RS2
03 - or r5,r6,r7
MUX
Next PC
04 - sub r8,r9,r10
WB Data
Ciclo 7
Sign
Extend
RD
RD
RD
Instr. 06 – add r1,r2,r3
Instr. 07 – and r2,r3,r4
Instr. 08 – or r5,r6,r7
Instr. 09 – sub r8,r9,r10
Instr. 10 – xor r11,r12,r13
CS252-s06, Lec 02-intro
24
Determinou o
endereço de A
A
08 - or r5,r6,r7
07 - and r2,r3,r4
Next SEQ PC
Next SEQ PC
Adder
4
Zero?
RS1
MUX
MEM/WB
Data
Memory
Instr. 05 – xor r11,r12,r13
EX/MEM
Instr. 04 – sub r8,r9,r10
Imm
ALU
Instr. 03 – or r5,r6,r7
MUX MUX
Instr. 02 – and r2,r3,r4
ID/EX
Instr. 01 – add r1,r2,r3
Reg File
IF/ID
Memory
Address
RS2
05 - xor r11,r12,r13 04 - sub r8,r9,r10
MUX
Next PC
06 - beqz r1, i10
WB Data
Ciclo 8
Sign
Extend
RD
RD
RD
Instr. 06 – beqz r1, i10
Instr. 07 – and r2,r3,r4
Instr. 08 – or r5,r6,r7
Instr. 09 – sub r8,r9,r10
Instr. 10 – xor r11,r12,r13
CS252-s06, Lec 02-intro
25
Determinou o
endereço de A
A
10 - xor r11,r12,r13
07 - and
r2,r3,r4
anulada
Next SEQ PC
Next SEQ PC
Adder
4
MUX
MEM/WB
Data
Memory
EX/MEM
Instr. 05 – xor r11,r12,r13
ALU
Instr. 04 – sub r8,r9,r10
Imm
MUX MUX
Instr. 03 – or r5,r6,r7
ID/EX
Instr. 02 – and r2,r3,r4
Reg File
IF/ID
Memory
Address
Instr. 01 – add r1,r2,r3
05 - xor r11,r12,r13
Zero?
RS1
RS2
06 - beqz r1, i10
MUX
Next PC
08 - or
r5,r6,r7
anulada
WB Data
Ciclo 9
Sign
Extend
RD
RD
RD
Instr. 06 – beqz r1, i10
Instr. 07 – and r2,r3,r4
Instr. 08 – or r5,r6,r7
Instr. 09 – sub r8,r9,r10
Instr. 10 – xor r11,r12,r13
CS252-s06, Lec 02-intro
26
Pipeline melhorado
Instruction
Fetch
Memory
Access
Write
Back
Adder
Adder
MUX
Next
SEQ PC
Next PC
Zero?
RS1
MUX
MEM/WB
Data
Memory
EX/MEM
ALU
MUX
ID/EX
Imm
Reg File
IF/ID
Memory
Address
RS2
WB Data
4
Execute
Addr. Calc
Instr. Decode
Reg. Fetch
Sign
Extend
RD
RD
RD
• Perda de apenas um ciclo se o desvio for tomado
CS252-s06, Lec 02-intro
27
Four Branch Hazard Alternatives
#1: Stall until branch direction is clear
#2: Predict Branch Not Taken
–
–
–
–
–
Execute successor instructions in sequence
“Squash” instructions in pipeline if branch actually taken
Advantage of late pipeline state update
47% MIPS branches not taken on average
PC+4 already calculated, so use it to get next instruction
#3: Predict Branch Taken
– 53% MIPS branches taken on average
– But haven’t calculated branch target address in MIPS
» MIPS still incurs 1 cycle branch penalty
» Other machines: branch target known before outcome
CS252-s06, Lec 02-intro
28
Four Branch Hazard Alternatives
#4: Delayed Branch
– Define branch to take place AFTER a following instruction
branch instruction
sequential successor1
sequential successor2
........
sequential successorn
branch target if taken
Branch delay of length n
– 1 slot delay allows proper decision and branch target
address in 5 stage pipeline
– MIPS uses this
CS252-s06, Lec 02-intro
29
Escalonando Branch Delay Slots
A. From before branch
add $1,$2,$3
if $2=0 then
delay slot
becomes
B. From branch target
sub $4,$5,$6
add $1,$2,$3
if $1=0 then
delay slot
becomes
if $2=0 then
add $1,$2,$3
add $1,$2,$3
if $1=0 then
sub $4,$5,$6
C. From fall through
add $1,$2,$3
if $1=0 then
delay slot
sub $4,$5,$6
becomes
add $1,$2,$3
if $1=0 then
sub $4,$5,$6
• A é a melhor escolha, pois enche o slot e reduz a contagem de instruções
(CI)
• Em B, a instrução sub pode precisar ser copiada, aumentando a CI
• Em B e C, não pode haver problemas em executar a sub quando o desvio
não é tomado
CS252-s06, Lec 02-intro
30
Delayed Branch
• Compiler effectiveness for single branch delay slot:
– Fills about 60% of branch delay slots
– About 80% of instructions executed in branch delay slots useful
in computation
– About 50% (60% x 80%) of slots usefully filled
• Delayed Branch downside: As processor go to
deeper pipelines and multiple issue, the branch
delay grows and need more than one delay slot
– Delayed branching has lost popularity compared to more
expensive but more flexible dynamic approaches
– Growth in available transistors has made dynamic approaches
relatively cheaper
CS252-s06, Lec 02-intro
31
Evaluating Branch Alternatives
Pipeline speedup =
Pipeline depth
1 +Branch frequency Branch penalty
Assume 4% unconditional branch, 6% conditional branchuntaken, 10% conditional branch-taken
Scheduling
Branch CPI speedup v. speedup v.
scheme
penalty
unpipelined
stall
Stall pipeline
3 1.60
3.1
1.0
Predict taken
1 1.20
4.2
1.33
Predict not taken
1 1.14
4.4
1.40
Delayed branch
0.5 1.10
4.5
1.45
CS252-s06, Lec 02-intro
32
Problems with Pipelining
• Exception: An unusual event happens to an
instruction during its execution
– Examples: divide by zero, undefined opcode
• Interrupt: Hardware signal to switch the
processor to a new instruction stream
– Example: a sound card interrupts when it needs more audio
output samples (an audio “click” happens if it is left waiting)
• Problem: It must appear that the exception or
interrupt must appear between 2 instructions (Ii
and Ii+1)
– The effect of all instructions up to and including Ii is totalling
complete
– No effect of any instruction after Ii can take place
• The interrupt (exception) handler either aborts
program or restarts at instruction Ii+1
CS252-s06, Lec 02-intro
33
Precise Exceptions in Static Pipelines
Key observation: architected state only
change in memory and register write stages.
Outra alternativa para reduzir o impacto
dos desvios condicionais
• Predição de desvios!
• Mas, para compreender como
implementar, precisamos saber como
funcionam os caches!
CS252-s06, Lec 02-intro
35