Exemplo de arquitetura
registrador-registrador- MIPS
MIPS
• ISA – todas as instruções de 32 bits, em 3 formatos:
R
op
rs
rt
rd
I
op
rs
rt
16 bit address
J
op
funct
26 bit address
• Máquina RISC – aritmética registrador-registrador
• 32 registradores de 32 bits
• Memória endereçada por 32 bits, organizada em bytes – ou seja,
a diferença de endereçamento de uma palavra (32 bits) e outra, da
memória, é múltipla de 4.
230 words têm endereços de bytes 0, 4, 8, ... 232-4
Banco de 32 Registradores do MIPS
Notação: sempre usa $ como prefixo
$0
.
.
.
$31
Name Register number
$zero
0
$v0-$v1
2-3
$a0-$a3
4-7
$t0-$t7
8-15
$s0-$s7
16-23
$t8-$t9
24-25
$gp
28
$sp
29
$fp
30
$ra
31
Usage
the constant value 0
values for results and expression evaluation
arguments
temporaries
saved
more temporaries
global pointer
stack pointer
frame pointer
return address
Instruções típicas
• Instrução
R
Significado
add $s1,$s2,$s3
sub $s1,$s2,$s3
slt $s1,$s2,$s3
$s1 = $s2 + $s3
$s1 = $s2 – $s3
se $s2 < $s3 então $s1=1 senão $s1=0
I
lw $s1,100($s2) $s1 = Memory[$s2+100]
sw $s1,100($s2) Memory[$s2+100] = $s1
I
bne $s4,$s5,L
beq $s4,$s5,L
Próx. instr. é no Label se $s4< >$s5
Próx. instr. é no Label se $s4 = $s5
J
j Label
Próx. instr. é no Label
• Formatos:
R
6
op
I
op
J
op
5
rs
5
rt
rs
rt
5
5
rd
6
funct
16 bit address
26 bit address
Instruções aritméticas usando
operandos imediatos (constantes)
instrução
addi
andi
ori
slti
I
$29,
$29,
$29,
$t1,
significado
$29,
$29,
$29,
$s1,
4
6
4
2
$29 = $29+ 4
$29 = $29 and 6
$29 = $29 or 4
Se $s1 < 2 então $t1=1 senão $t1=0
Formato:
I
op
rs
rd
16 bits imediato
Modos de
Endereçamento
1. Immediate addressing
imediato
op
rs
rt
Immediate
2. Register addressing
registrador
op
rs
rt
rd
...
funct
Registers
Register
3. Base addressing
memória
(dados)
memória
op
rs
rt
Byte
Halfword
4. PC-relative addressing
op
rs
rt
Memor y
Address
PC
(instrução)
+
Register
(instrução)
memória
Memor y
Address
+
Word
5. Pseudodirect addressing
op
Address
PC
Memor y
Word
Word
HARDWARE: Unidades funcionais necessárias
Mem. instrução
PC
Somador
Mem.dados
Extensão de
sinal
Banco de registradores
ALU
Implementação de MIPS em um único ciclo
0
M
u
x
Add
Add
4
Instruction [31– 26]
Control
controle
Instruction [25– 21]
PC
Read
address
PC
Instruction
memory
Instruction [15– 11]
1
Shift
left 2
RegDst
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read
register 1
Instruction [20– 16]
Instruction
[31– 0]
ALU
result
0
M
u
x
1
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
Write
data
0
M
u
x
1
regs
Zero
ALU ALU
result
Write
data
Mem.
instrução
16
Instruction [15– 0]
Sign
extend
RegDst
1
0
X
X
ALUSrc
0
1
1
0
MemtoReg
0
1
X
X
Data
memory
32
ALU
control
Instruction [5– 0]
Instruction
R-format
lw
sw
beq
Read
data
Address
Reg Mem Mem
Write Read Write
1
0
0
1
1
0
0
0
1
0
0
0
Branch
0
0
0
1
Mem. dados
ALUOp1 ALUp0
1
0
0
0
0
0
0
1
1
M
u
x
0
Controle:- decodificação do opcode e geração dos sinais de controle
Inputs
ALU-control
ALUOp
opcode
Op5
control
Op4
Op3
Op2
Op1
Op0
ALU control block
ALUOp0
ALUOp1
F2
F (5– 0)
Operation1
Operation
Iw
sw
beq
RegDst
ALUSrc
MemtoReg
F1
Operation0
F0
R-format
Operation2
RegWrite
MemRead
MemWrite
Branch
ALUOp1
ALUOpO
sinais de controle
F3
Outputs
Fluxo numa instrução aritmética (R-format)
0
M
u
x
Add
Add
RegDst
4
Instruction [31– 26]
Control
Instruction [25– 21]
PC
Read
address
Instruction
[31– 0]
Instruction
memory
Instruction [15– 11]
0
M
u
x
1
1
Shift
left 2
RegDst
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
ALUOp
Memto
Reg
ALUSrc
Read
register 1
Instruction [20– 16]
ALU
result
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
M
u
x
1
Write
data
Zero
ALU ALU
result
Write
data
16
Instruction [15– 0]
Sign
extend
Read
data
Address
Data
memory
32
ALU
control
Instruction [5– 0]
Instruction
R-format
lw
sw
beq
RegDst
1
0
X
X
ALUSrc
0
1
1
0
MemtoReg
0
1
X
X
Reg Mem Mem
Write Read Write
1
0
0
1
1
0
0
0
1
0
0
0
Branch
0
0
0
1
ALUOp1 ALUp0
1
0
0
0
0
0
0
1
1
M
u
x
0
opcode
Circuito de Controle (decodificação do opcode e
geração dos sinais de controle)
0 Inputs
0 Op5
Op4
0 Op3
0 Op2
0 Op1
0 Op0
R-format
Iw
sw
beq
RegDst
ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
ALUOp1
ALUOpO
Instruction
R-format
lw
sw
beq
RegDst
1
0
X
X
ALUSrc
0
1
1
0
MemtoReg
0
1
X
X
Reg Mem Mem
Write Read Write
1
0
0
1
1
0
0
0
1
0
0
0
Branch
0
0
0
1
sinais de controle
Outputs
1
0
0
1
0
0
0
1
0
ALUOp1
1
0
0
0
ALUp0
0
0
0
1
Fluxo para a instrução lw
0
M
u
x
Add
Add
4
Instruction [31– 26]
Control
Instruction [25– 21]
PC
Read
address
Instruction
memory
Instruction [15– 11]
1
Shift
left 2
RegDst
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read
register 1
Instruction [20– 16]
Instruction
[31– 0]
ALU
result
0
M
u
x
1
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
Zero
ALU ALU
result
0
M
u
x
1
Write
data
Write
data
16
Instruction [15– 0]
Sign
extend
RegDst
1
0
X
X
ALUSrc
0
1
1
0
MemtoReg
0
1
X
X
Data
memory
1
M
u
x
0
32
Instruction [5– 0]
Instruction
R-format
lw
sw
beq
Read
data
Address
Reg Mem Mem
Write Read Write
1
0
0
1
1
0
0
0
1
0
0
0
ALU
control
LMD (Load Mem. Data)
Branch
0
0
0
1
ALUOp1 ALUp0
1
0
0
0
0
0
0
1
opcode
Circuito de Controle (para lw)
1
0
0
0
1
1
Inputs
Op5
Op4
Op3
Op2
Op1
Op0
R-format
Iw
sw
beq
RegDst
ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
ALUOp1
ALUOpO
Instruction
R-format
lw
sw
beq
RegDst
1
0
X
X
ALUSrc
0
1
1
0
MemtoReg
0
1
X
X
Reg Mem Mem
Write Read Write
1
0
0
1
1
0
0
0
1
0
0
0
Branch
0
0
0
1
sinais de controle
Outputs
0
1
1
1
1
0
0
0
0
ALUOp1
1
0
0
0
ALUp0
0
0
0
1
Fluxo para a instrução sw
0
M
u
x
Add
Add
4
Instruction [31– 26]
Control
Instruction [25– 21]
PC
Read
address
Instruction
memory
Instruction [15– 11]
1
Shift
left 2
RegDst
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read
register 1
Instruction [20– 16]
Instruction
[31– 0]
ALU
result
0
M
u
x
1
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
M
u
x
1
Write
data
Zero
ALU ALU
result
Write
data
16
Instruction [15– 0]
Sign
extend
RegDst
1
0
X
X
ALUSrc
0
1
1
0
MemtoReg
0
1
X
X
Data
memory
1
M
u
x
0
32
Instruction [5– 0]
Instruction
R-format
lw
sw
beq
Read
data
Address
Reg Mem Mem
Write Read Write
1
0
0
1
1
0
0
0
1
0
0
0
ALU
control
SMD – Store Mem. Data
Branch
0
0
0
1
ALUOp1 ALUp0
1
0
0
0
0
0
0
1
opcode
Circuito de Controle (para sw)
1
0
1
0
1
1
Inputs
Op5
Op4
Op3
Op2
Op1
Op0
R-format
Iw
sw
beq
RegDst
ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
ALUOp1
ALUOpO
Instruction
R-format
lw
sw
beq
RegDst
1
0
X
X
ALUSrc
0
1
1
0
MemtoReg
0
1
X
X
Reg Mem Mem
Write Read Write
1
0
0
1
1
0
0
0
1
0
0
0
Branch
0
0
0
1
sinais de controle
Outputs
0
1
0
0
0
1
0
0
0
ALUOp1
1
0
0
0
ALUp0
0
0
0
1
Fluxo para a instrução beq
0
M
u
x
Add
Add
4
Instruction [31– 26]
Control
Instruction [25– 21]
PC
Read
address
Instruction
memory
Instruction [15– 11]
1
Shift
left 2
RegDst
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read
register 1
Instruction [20– 16]
Instruction
[31– 0]
ALU
result
0
M
u
x
1
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
M
u
x
1
Write
data
Zero
ALU ALU
result
Write
data
16
Instruction [15– 0]
Sign
extend
Read
data
Address
Data
memory
32
ALU
control
Instruction [5– 0]
Instruction
R-format
lw
sw
beq
RegDst
1
0
X
X
ALUSrc
0
1
1
0
MemtoReg
0
1
X
X
Reg Mem Mem
Write Read Write
1
0
0
1
1
0
0
0
1
0
0
0
Branch
0
0
0
1
ALUOp1 ALUp0
1
0
0
0
0
0
0
1
1
M
u
x
0
opcode
Circuito de Controle (para beq)
0
0
0
1
0
0
Inputs
Op5
Op4
Op3
Op2
Op1
Op0
R-format
Iw
sw
beq
RegDst
ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
ALUOp1
ALUOpO
Instruction
R-format
lw
sw
beq
RegDst
1
0
X
X
ALUSrc
0
1
1
0
MemtoReg
0
1
X
X
Reg Mem Mem
Write Read Write
1
0
0
1
1
0
0
0
1
0
0
0
Branch
0
0
0
1
sinais de controle
Outputs
0
0
0
0
0
0
1
0
1
ALUOp1
1
0
0
0
ALUp0
0
0
0
1
Fluxo de dados multiciclo – usando uma única
memória para instruções e dados
ALUSrcA
PC
0
M
u
x
1
IorD
Instruction
[25– 21]
Address
Memory
MemData
Write
data
Instruction
[20– 16]
Instruction
[15– 0]
Instruction
register
Instruction
[15– 0]
Memory
data
register
RegDst
Read
Read
data
1
register 2
Registers
Write
Read
register data 2
0
M
Instruction u
x
[15– 11]
1
0
M
u
x
1
0
M
u
x
1
Read
register 1
A
B
MemtoReg
ALU ALU
result
0
4
Write
data
Zero
1M
u
2 x
3
ALUSrcB
16
Sign
extend
32
Shift
left 2
ALUOut
Passo 1: Busca da instrução (Instruction Fetch)
• Usar o PC para a leitura da instrução e carga da mesma no
registrador de instrução (Instruction Register).
• Incrementar o valor do PC por 4 e carregar o resultado no PC.
IR = Memory[PC];
PC = PC + 4;
Podemos obter os valores dos sinais de controle?
Passo 2: Decod. da Instrução e Busca de
Registradores
• Leitura dos registradores rs e rt
• Computar o endereço de branch no caso da instrução de branch
A = Reg[IR[25-21]];
B = Reg[IR[20-16]];
ALUOut = PC + (sign-extend(IR[15-0]) << 2);
• Preparando para acionar as linhas de controle baseadas no tipo
de instrução
(a instrução está sendo "decodificada" na lógica de controle)
Passo 3 (dependente da instrução)
• ALU está realizando uma das três funções, baseadas no tipo de
instrução
• Referência à memória:
ALUOut = A + sign-extend(IR[15-0]);
• R-type:
ALUOut = A op B;
• Branch:
if (A==B) PC = ALUOut;
Passo 4 (R-type ou acesso à memória)
• Acesso à memória através de loads e stores
MDR = Memory[ALUOut];
ou
Memory[ALUOut] = B;
• Fim das instruções R-type
Reg[IR[15-11]] = ALUOut;
A escrita é realizada no fim do ciclo, na borda
Passo 5 (Write-back, para instrução load)
• Reg[IR[20-16]]= MDR;
Fim da instrução load!