Chapter 6: Real-Time Digital Time-Varying
Harmonics Modeling and Simulation Techniques
Tutorial on Harmonics Modeling and Simulation
Presenter: Paulo F RIbeiro
Contributors: L-F. Pak, V. Dinavahi, G. Chang, M.
Steurer, S. Suryanarayanan, P. Ribeiro
1
IEEE PES General Meeting, Tampa FL
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Conferência Brasileira de Qualidade de Energia
Santos, São Paulo, Agosto 5-8, 2007
Need for Sophisticated Tools for Power
Quality (PQ) Studies
 Proliferation of nonlinear and time-varying loads has led to
significant power quality concerns.
 Traditionally, time-varying harmonics were studies using
statistical and probabilistic methods for periodic harmonics.
 Cannot describe random characteristics
 Cannot capture the reality of physical phenomena.
 A time-dependent spectrum is needed to compute the
local power-frequency distribution at each instant.
 Significant advances in equipment for PQ monitoring,
waveform generation, disturbance detection, and mitigation.
 Digital signal processing is widely used.
 Sophisticated power electronic controllers are used for
PQ mitigation.
 Need for testing and validation of such equipment.
 Real-time digital simulation as an advanced tool for PQ
analysis and mitigation.
2
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Real-Time Harmonic Modeling and Simulation
Techniques

Wave Digital Filters

Discrete Wavelet Transform

Real-Time Electromagnetic Transient Network
Solution

Real-Time Digital Simulators
 RTDS



PC-Cluster Based Simulators
HYPERSIM
DSPACE
3
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Wave Digital Filters
 Digital Signal Processing tool that
transforms analog networks into
topologically equivalent digital filters
Analog
Element
Realization by WDFs
Port
Resistance
Incident and
Reflected waves
A
 Synthesis is based on wave network
characterization
(a)
R
B
0
A
 Designed to attain low-sensitivity
structures to quantization errors in
digital filter coefficients
(b)
 Powerful technique for simulating power
system harmonics and transients
4
(c)
2L
T
T
2C
T
B
-1
A
T
B
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Discrete Wavelet Transform
 Time-Frequency
representation of time varying
signals.
 Wavelet analysis starts by
adopting a prototype function.
Time Analysis is done with a
contracted
high-frequency
prototype. Frequency analysis
is done using a dilated lowfrequency prototype.
Operator representation theory
is used to model electrical
componenets
in
discrete
wavelet domain
v(t )  L
L  DTW
+
di(t )
dt
i(t )  C
cv  0
L  i(0)  VL0W
- + -
VW  L  DTW IW  L  i(0)  VL0W
Transient Inductor
Model
5
(b)
1
INTW
C
+
VWS  L  DSW  I SW
Steady-state Inductor
Model
dv(t )
dt
ci  0 v(0)  k j
v(0)  VC 0W
VW  v(0)  VC 0W 
+ - 1
C
+
INTW  IW
Transient Capacitor
Model
+ WVS 
(c)
1
IN DSW  I S
C
+ - -
1
IN SW  I SW
C
Steady-state Capacitor
Model
IEEE PES General Meeting, Tampa FL
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PC-Cluster Based Real-Time Digital
Simulator
 Real-Time eXperimental LABoratory (RTX-LAB) at the University of
Alberta.
Hosts
Gigabit
HS1 HS2 OK1 OK2 PS
1 2 3 4 5 6 7 8 9101112
COLACTSTA-
Ethernet
CONSOLE
InfiniBand
Link
1X
13X
24
12X
7X
18 19X
6X
Closed-Loop
Controller Testing
STATUS
green = enabled, link OK
flashing green=disabled,link OK
off = link fail
TCVR1 2 3 4 5 6 7 8 9 10 11 12
1 2 3 4 5 6 7 8 9 10 11 12
1314 1516 17 18 1920 21 22 23 24
1314 1516 17 18 1920 21 22 23 24
Module
Packet
Status
Packet
Status
25X
26X
UNIT
1 2
3 4
24 26Packet 5 6
24 26Status 7 8
10BaseTX/100Base TX
HiNet WS 4400
SIEMENS
Target Cluster
6
Hardware-in-the-Loop
Machine Testing
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Features of the RTX-LAB Simulator
 Fully Flexible and scalable
 Fast FPGA based analog and digital I/O and
high intra-node communication speed
 Varity of synchronization options
 Compatible
with MATLAB/SIMULINK and
other programming languages
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Hardware Architecture of the RTX-LAB
Simulator
FPGA 1
(Signal Conditioning)
 Two types of computers- Targets and Hosts
 Targets
are dual CPU based 3.0 GHZ Xeon,
work as the main simulation engine and
facilitates FPGA based I/Os
I
N
F
I
N
I
B
A
N
D
Cluster Node 1
(Dual XEON)
S
I
G
N
A
L
L
I
N
K
W
I
R
E
Memory
CPU
2
Cluster Node 2
(Dual XEON)
CPU
1
 Hosts are 3.00 GHZ Pentium IV, used for model
development, compilation and loading of the
model to the cluster
CPU
1
Shared
G
I
G
A
B
I
T
Host 1
Shared
Memory
CPU
2
Cluster Node n
(Dual XEON)
CPU
1
External
Hardware
Shared
Memory
CPU
2
FPGA n
(Signal Conditioning)
Host 2
E
T
H
E
R
N
E
T
Host n
Hosts
External
Hardware
Target Cluster
8
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Software Architecture of the RTX-LAB
Simulator
External Hardware
 Target OS- RedHawk Linux
 Host OS- Windows XP
 Model Development-
Model Development
Intra-Node
Communication
Cluster Node
Signal-Wire
Hardware Communication
Real-Time
Network
Interface
- A/D and D/A Conversion
- Signal Conditioning
- Fast DMA Burst Transfer
Using FPGA
MATLAB/SIMULINK
Other programming
Languages C, C++
SIMULINK
Infiniband
Real-Time OS
CBB
(Constant
Bi-Sectional
Bandwidth)
System Model
Control Model
S-function
Custom Solver
Compilation
Real-Time
Workshop (RTW)
Real-Time
Communication
GUI
- Real-Time Linux
TCP/IP Scheduling
- CPU Shielding
SIMULINK
- Parallel Simulation
Data Acquisition LabView
- Multi-Rate Simulation
I/O
Python
- Real-Time Communication
Management
Others
Target Cluster
9
Hosts
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Communication Links in the RTX-LAB
Simulator
 I/O signals from real-hardware are
 InfiniBand Link
connected through FPGA based I/Os
Maximum Throughput- 10Gbps
 Xilinx Virtex-II Pro is used
 Shared Memory
100 MHZ operation speed
bus speed – 2.67Gbps
 Signal Wire Link
Data Transfer rate-1.2Gbps
 Gigabit Ethernet link
Transfer Rate- Up to 1Gbps
10
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Subsystems and Synchronization in the RTXLAB Simulator
User
Interface
Comp.
Wait
for I/O
Sync
Recv
Send
m
I/O
One time-step
ACQ
Master
Subsystem
Send
One time-step
Iabc
Comp.
ACQ
Electrical
system
ACQ
(Subsystem 3)
I/O Comp.
Wait for Sync I/O Comp.
Wait for Sync
: Computation
: Acquisition
One time-step
One time-step
: Receive
(a)
: Synchronization
Recv
(Subsystem 2)
Comp
ACQ
Recv
Sync
ACQ
Control
system
Gating
Pulses
Console
Recv
(Subsystem 1)
Master
Send
Slave
ACQ
External Hardware
Wait
for
Sync
Target Cluster
I/O
Host 1
Recv
One time-step
Hosts
I/O
ACQ
Cluster
Node 2
Comp.
Cluster
Node 1
Comp.
Te*
Send
m*
Slave
Subsystem
One time-step
(b)
11
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Case Study 1: Time-Varying Harmonic Analysis on
the RTX-LAB Real-Time Digital Simulator
Power grid
VL-L = 220 kV
HV/MV Transformer
MV/LV Transformer
220 kV / 45 kV
45 kV / 600 V
Y
RS = 0.001 p.u.
LS = 0.005 p.u.
Y
RT1 = 0.002 p.u.
LT1 = 0.55 p.u.
RT2 = 0.002 p.u.
LT2 = 0.55 p.u.
Single-line Diagram of the Arc Furnace
Installation
12
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Case Study 1: Time-Varying Harmonic Analysis on
the RTX-LAB Real-Time Digital Simulator
Phase Current Measurement
Stochastic
Component
Generation
Connection
to MV/LV
Transformer
+
Deterministic
Component
Generation
+
Chaotic
Component
Generation
Controlled
Voltage Source
Schematic of the Arc Furnace Model
13
IEEE PES General Meeting, Tampa FL
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Case Study 1: Time-Varying Harmonic Analysis on
the RTX-LAB Real-Time Digital Simulator
1st
3rd
5th
7th
9th
Voltage and Current for the Arc Furnace
14
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Case Study 1: Time-Varying Harmonic Analysis on
the RTX-LAB Real-Time Digital Simulator
1st
5th
7th
Voltage at the Primary Winding of the MV/LV Transformer
15
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Case Study 1: Time-Varying Harmonic Analysis on
the RTX-LAB Real-Time Digital Simulator
1st
5th
Current in the Primary Winding of the MV/LV Transformer
16
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RTDS at CAPS
•
•
•
•
•
•
Provides time domain solution in real time with typical time step sizes around 50 μs using the
Dommel (EMTP) algorithm
Features dual time step (<2 μs) capability for PE simulations
Allows up to 54 electrical nodes per rack, but subsystems can be connected through cross-rack
elements (transmission lines, etc.)
Large library of power system and control component models (like EMTDC)
> 350 parallel DSPs
> 2500 analog outputs and over 200 digital inputs and outputs
RPC – Network Solution
IRC – Inter-rack Communication
WIF – Workstation Interface
3PC – Controls, system dynamics
GPC – Network solution, fast-switching
converters
Rack 1
Rack 2
Rack 3
Rack 4
Rack 5
Rack 6
Rack 7
Rack 8
Rack 9
Rack 10
Rack 11
Rack 12
Rack 13
Rack 14
3PC-1
3PC-2
3PC-1
3PC-2
3PC-1
3PC-2
3PC-1
3PC-2
3PC-1
3PC-2
3PC-1
3PC-2
3PC-1
3PC-2
3PC-1
3PC-2
3PC-1
3PC-2
3PC-1
3PC-2
3PC-1
3PC-2
3PC-1
3PC-2
3PC-1
3PC-2
3PC-1
3PC-2
3PC-3
3PC-4
3PC-5
3PC-6
3PC-7
3PC-3
3PC-4
3PC-5
3PC-6
3PC-7
3PC-3
3PC-4
3PC-5
3PC-6
3PC-7
3PC-3
3PC-4
3PC-5
3PC-6
3PC-7
3PC-8
3PC-9
3PC-10
3PC-8
3PC-9
DOPTO-1
3PC-8
3PC-9
3PC-10
3PC-8
3PC-9
DOPTO-1
DOPTO-1
3PC-10
DOPTO-2
DOPTO-1
3PC-10
DOPTO-2
RPC
IRC
WIF
RPC
IRC
WIF
RPC
IRC
WIF
RPC
IRC
WIF
3PC-3
3PC-4
3PC-5
3PC-6
3PC-7
3PC-3
3PC-4
3PC-5
3PC-6
3PC-7
3PC-3
3PC-4
3PC-5
3PC-6
3PC-7
3PC-3
3PC-4
3PC-5
3PC-6
3PC-7
3PC-3
3PC-4
3PC-5
3PC-6
3PC-7
3PC-8
DOPTO-1
3PC-8
3PC-8
DOPTO-1
3PC-8
3PC-8
DOPTO-1
GPC
GPC
IRC
WIF
IRC
WIF
3PC-3
3PC-4
3PC-5
3PC-6
3PC-3
3PC-4
3PC-5
3PC-6
3PC-3
3PC-4
3PC-5
3PC-6
3PC-3
3PC-4
3PC-5
3PC-6
GPC-1
GPC-1
GPC-1
GPC-1
GPC-1
GPC-2
GPC-2
GPC-2
GPC-2
GPC-2
GPC-3
IRC
WIF
IRC
WIF
IRC
WIF
IRC
WIF
RPC
RPC
RPC
GPC
GPC
3PC-3
3PC-4
3PC-5
3PC-6
RPC
RPC
IRC
WIF
IRC
WIF
17
GPC
IRC
WIF
IRC
WIF
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14 Rack RTDS Installation at CAPS
•
•
•
Largest RT simulator installation in any university worldwide
Systems of up to 250 three-phase buses
Sufficient high-speed I/O to enable realistic HIL and PHIL experiments
18
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(Controller) hardware in loop (HIL) and
power hardware in loop PHIL
External Hardware
Real Time Digital Simulator
S ystem Data in Simulation
D/A
A/D
Hardware response
Universal
c ontroller
P rotection relay
M
M
G
G
AC/AC power converter
(Motor Drive)
Controller
G
DC Load
Relay
Simulated rest of system
19
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Case Study 2: Power Quality Sensitivity Study of a
Controller on the RTDS
Real-Time Digital Simulation on RTDSTM
Power Grid
Distribution Transformer
VL-L = 12.47 kV
12.47 kV / 480 V
Y
6-pulse
Thyristor Rectifier
+ Industry
DC
Load
Y
-
Rsource = 0.05 p.u.
Lsource = 0.005 p.u.
RT = 0.05 p.u.
LT = 0.005 p.u.
Voltage
Sensing
Gating
Pulses
RL =0.48 
LL =1.00 mH
Enerpro® FCOF 6100 Three-Phase
Thyristor Firing Board
Tested Hardware
Schematic of the Industrial Distribution System and
Rectifier Load
20
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P rim a ry volt age (kV )
Case Study 2: Power Quality Sensitivity Study of a
Controller on the RTDS
10
5
0
-5
-10
D C v oltage (k V)
0.05
0.1
0.15
0.2
0.25
0.1
0.15
Time (s)
0.2
0.25
0.4
0.3
0.2
0.1
0
0.05
Single-phase Voltage Sag (40% reduction, no phase
shift) and its Impact on Rectifier DC Output
21
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P ri mary v oltage (k V)
Case Study 2: Power Quality Sensitivity Study of a
Controller on the RTDS
10
5
0
-5
-10
D C voltag e (kV )
0.05
0.1
0.15
0.2
0.25
0.1
0.15
Time (s)
0.2
0.25
0.4
0.3
0.2
0.1
0
0.05
Phase-Shifted Single-phase Voltage Sag (40% reduction)
and its Impact on Rectifier DC Output
22
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Case Study 3: Harmonic Distortion on the RTDS
Shipboard Power System
Voltage (kV)
Voltage (kV)
5
0
Voltage Magnitued (kV)
-5
0
0.01
0.02
0.03
0.04
0.05
time (s)
0.1
0.05
0
0
500
1000
frequency (Hz)
23
1500
2000
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Case Study 4: A HIL Simulation for Studying the
Transient Behavior of Wind DG
User
Interaction
Rotor torque
Substation
Line Impedance
To change the
stiffness of the grid
Local
Load
iGT
G
M
Wind Speed
VSD
For reactive
power
Capacitor compensation
Bank
Simulated Wind
Turbine Model
VSD
System Simulated in
Real Time Simulator
M
G
24
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Case Study 4: A HIL Simulation for Studying the
Transient Behavior of Wind DG
Simulation generator current
current (kA)
0.1
0.05
0
-0.05
-0.1
0
0.02
0.04
0.06
0
2
4
6
0.08
0.1
0.12 0.14
time (s)
Normalized FFT of the Current
0.16
0.18
0.2
16
18
20
Magnitude
0.1
0.05
0
8
10
12
Order of Harmonic
25
14
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Conclusions
 With rising number of time-varying and nonlinear loads sophisticated
harmonics modeling and simulation tools are needed.
 A combination of fast topological methods and powerful real-time
simulators can overcome limitations of off-line simulation tools.
 A general review of current off-line harmonic modeling and
simulation tools is presented.
 Currently available real-time simulation techniques are discussed.
 Two real-time case studies: arc furnace modeling and power quality
sensitivity of a controller, are presented.
26
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