SET Fault Tolerant
Combinational Circuits
Based on Majority Logic
Álisson Michels
Lorenzo Petroli
Carlos Lisbôa
Fernanda Kastendsmidt
Luigi Carro
DFT 2006
Washington, DC, USA
Embedded Systems Laboratory and Electrical Engineering Department
Informatics Institute and Engineering School
Federal University of Rio Grande do Sul
Porto Alegre – RS – Brazil
What is Wrong with TMR ?
• TMR does not protect against two faults
affecting different modules
• When a single fault occurs in the voter circuit,
the voter output may be wrong
Module 1
wrong output
Module 2
correct output
Module 3
wrong output
Carlos Lisbôa
Module 1
V
O
T
E
R
wrong output
correct output
Module 2
correct output
Module 3
correct output
DFT 2006 - October, 4-6, 2006
V
O
T
E
R
correct output ?
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Fault-tolerant analog voter
• transient pulse model:
double exponential
• injection of faults
• no effect on voter output
Carlos Lisbôa
DFT 2006 - October, 4-6, 2006
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Use of majority gates in AOI logic
• majority(a, b, 0) = a.b + a.0 + b.0 = a.b
(AND gate)
• majority(a, b, 1) = a.b + a.1 + b.1 = a.b + a + b = a + b (OR gate)
• the analog comparator can be used as a fault-tolerant inverter
AND gate
Carlos Lisbôa
OR gate
DFT 2006 - October, 4-6, 2006
inverter
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Sample implementation: full adder
Classic TMR implementation:
- 3 standard AOI full adder
modules
- 1 digital voter per output bit
Carlos Lisbôa
Proposed solution:
- single full adder module
- majority gates used to implement
AND/OR functions
- analog comparators used to
implement majority gates and
inverters
DFT 2006 - October, 4-6, 2006
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Area Comparison
(32 nm technology)
2
Circuit
Area (nm )
Relative Area
Classic TMR
8,744,960
1.00
Analog MGs
5,581,310
0.64
The proposed solution brings a 36%
reduction in area, when compared to
the classic TMR implementation
Carlos Lisbôa
DFT 2006 - October, 4-6, 2006
6
Thank You !
For more details,
come and see the poster !
Contact: [email protected]
Carlos Lisbôa
DFT 2006 - October, 4-6, 2006
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