University of Sao Paulo
DESIGN, FABRICATION AND
ELETRICAL CHARACTERIZATION OF
SOI FINFET TRANSISTORS
Prof. Dr. João Antonio Martino
Professor Titular
Departamento de Engenharia de Sistemas Eletrônicos
Escola Politécnica da Universidade de São Paulo, Brasil
University of Sao Paulo
DESIGN, FABRICATION AND
ELETRICAL CHARACTERIZATION OF
SOI FINFET TRANSISTORS
FAPESP Thematic Project
3 Universities: USP, UNICAMP, FEI
Group leaders:
Prof. Dr. João Antonio Martino (USP)
Prof. Dr. Sebastião G. dos Santos Filho (USP)
Prof. Dr. Antonio Carlos Seabra (USP)
Prof. Dr. José Alexandre Diniz (UNICAMP)
Prof. Dr. Marcelo Antonio Pavanello (FEI)
University of Sao Paulo
Keep increase of the number of components.
Cost per components decreases!
S. Deleonibus, “Electronics Device Architectures for the Nano-CMOS Era,” Pan Standford Publ., 2009
MOORE’S LAW (Gordon Moore – Intel)
G.E. Moore, “Cramming more components onto integrated circuits,” Electronics Mag., vol. 38, pp. 114-117, 1965.
University of Sao Paulo
Microelectronic Revolution Example
Intel 8008 (1972)
200 KHz
3.300 transistors
13 mm2
30 year
X 12.000
Intel Pentium 4 (2002)
2,2 GHz
42.000.000 transistors
146 mm2
≈Double each 2 years  MOORE’S LAW
University of Sao Paulo
Microelectronic Laboratory at USP
University of Sao Paulo
Clean Room Facilities
Microelectronic Laboratory at USP
University of Sao Paulo
Measurements Rooms
Microwave Measurement Systems
Optical Measurements Systems
Devices Characterization Laboratory
Circuit Cell = Transistor
University of Sao Paulo
Bulk MOSFET Transistor (Standard)
Gate
IDS
VDS=Low
Drain
Source Metal
Oxide
N+
N+
P
IDS
Bulk
IDS
Triode
D
G
VDS
VGS
VTn
S
VGS
Saturation VGS3>VGS2
VGS2
VGS1
VDS
Circuit Cell = Transistor
University of Sao Paulo
Bulk MOSFET Transistor ( Polysilicon Gate )
Gate
Source
Metal
Oxide
N+
Gate
(G)
Drain
N+
P
Source
(S)
Drain
(D)
Bulk
Fabricated at Polytechnic School – University of São Paulo
Master Degree – João Antonio Martino (1984)
University of Sao Paulo
Polysilicon Gate NMOS Technology
Brazil (USP)
Dimensions: 3mm x 3mm
4 Resistors
5 Capacitors
8 Transistors nMOS
1 Diode
1 Ring Oscilator
(31 stages)
2 Inverters
2 Adders (Full and Half)
(J.A.Martino – Master degree - USP - 1984)
Transistor
CMOS Technology - Brazil (USP)
University of Sao Paulo
Dimensions: 3mm x 3mm
7 Van der Pauw structures
e 2 Resistors
3 Kelvin structures
5 Capacitors
20 Transistors nMOS
20 Transistors pMOS
6 Diodes
1 Ring Oscilator(31 stages)
3 Inverters
Transistors
(J.A.Martino – Ph.D - USP - 1988)
SOI CMOS Technology (0.5 µm)
University of Sao Paulo
IMEC/Belgium
Dimension:10mm x 10mm
• 221 structures
• more
than
1000
terminals
• Transistor array from
L=10µm to 0.4µm
(J.A.Martino - Livre Docência - USP/IMEC-Belgium - 1998)
University of Sao Paulo
SOI CMOS Technology –Submic.
(0.1 µm) - IMEC/Belgium
Gate (VGF)
Drain (VD)
Source (VS)
N
N+
P+
P+
N
P
Buried Oxide
Substrate
Substrate (VGB)
Dimensions: 10mm x 10mm
Transistor arrays from
L=10µm to 0,08µm
N+
Gate
G
Gate
Evolution of MOS Transistors
University of Sao Paulo
D
S
Gate
Source
Drain
N+
N+
Gate
Gate
Drain
Source
Drain
P
BOX
Bulk
1 Gate “Single Gate”
SOI - Planar (IBM - 1998)
1 Gate “Single Gate”
Bulk - Planar (1966)
Source
ID
Buried Oxide
2 Gates “FinFET”
Vertical-3D (Intel - 2012)
Double Gate Transistors (FinFET or 3D)
University of Sao Paulo
Gate
Drain
Source
ID
Buried Oxide
University of Sao Paulo
Standard MOSFET versus FinFET(3D)
ADVANTAGES:
Key Features of FinFET devices:
 Better control of short channel effects
 SOI substrate;
 High current density (Higher
conduction current per unit area of
substrate)
 W Fin < 100nm; H Fin < 100nm;
 Quasi-ideal subthreshold slope
University of Sao Paulo
DESIGN, FABRICATION AND
ELETRICAL CHARACTERIZATION OF
SOI FINFET (3D) TRANSISTORS
FAPESP Thematic Project (2009-2013)
3 Universities: USP, UNICAMP, FEI
Goal of this work:
•Development of new step process
•First Fabrication of SOI FinFET in Brazil
•Characterization (Electrical and Physical)
•Formation of qualified Human resource
(Micro/Nanoelectronics)
University of Sao Paulo
Step by Step
Step 1: Design of the fabrication process of SOI FinFET
transistor (USP e UNICAMP).
Step 2: Development of new step process (USP and
UNICAMP).
Step 3: Fabrication of SOI FinFET : (USP and UNICAMP).
Step 4: Electrical Characterization of SOI FinFET.: (USP,
UNICAMP and FEI)
Step 5: Simulation of Numerical 3D SOI FinFET: (USP and FEI)
Step 6: Modeling of SOI FinFET: (FEI)
Step 7: Electrical Characterization of SOI FinFET as a function
of temperature : (USP e FEI)
Step 8: Reports: (USP , UNICAMP and FEI)
University of Sao Paulo
Special Characterizations (FEI and USP)
DUV 193 nm lithography with resist and oxide
hard mask trimming
Hfin=65 nm
1 nm interfacial oxide
2.3 nm HfSiON ALD deposition
5 nm TiN ALD deposition
SOI wafer with toxb=145 nm
100 nm polysilicon
Undoped channel
NiSi in all electrodes
*N. Collaert et al., Symp. VLSI Tech., p. 108, 2005.
University of Sao Paulo
Special Characterizations (FEI and USP)
• Electrical Characterization of
SOI FinFET as a function of
temperature
•Digital performance
•Analog performance
•Radiation effects
•Noise analysis
•Modeling (only FEI)
University of Sao Paulo
Special Characterizations (FEI and USP)
University of Sao Paulo
FinFET Fabrication with 3 masks
First Mask (Active Region Definition):
1. E-beam lithography in a modified SEM (definition
source/drain and fin line – max space resolution: 30nm);
2. Mask transfer for Si layer by RIE Plasma processing;
SiO2
Si
University of Sao Paulo
FinFET Fabrication with 3 masks
Mask 1 (Active Region Definition)
SiO2
Si
University of Sao Paulo
FinFET Fabrication with 3 masks
Second Mask (Gate Definition):
3. Gate oxidation (4.5nm);
4. Polycrystalline Silicon Deposition (500nm);
5. Poly-Si Phosphorous Doping;
6. E-beam lithography: Definition of Polycrystalline Silicon;
Poly-Si
Si
SiO2
University of Sao Paulo
FinFET Fabrication with 3 masks
Poly-Si
Si
gate SiO2
SOI SiO2
Gate Definition
Mask 2
University of Sao Paulo
FinFET Fabrication with 3 masks
Third Mask (Metal Definition):
7. Ionic Implantation (Source/Drain);
8. Annealing (Doping Activation);
9. Aluminum Deposition;
10. E-beam Lithography: Metal Definition;
Al
Si
Poly-Si
SOI SiO2
University of Sao Paulo
First FinFET Transistor (E-beam)
Al
Si
Poly-Si
SOI SiO2
Metal definition
Mask 3
Drain
Gate
Source
Electrical Characterization
University of Sao Paulo
WFIN= 100nm, HFIN= 100nm, tox= 4.5nm, tbox = 200nm, L = 3.5µm,
Gate electrode: Si-Poli
1.6µ
1.2µ
ID(A)
1.0µ
800.0n
1µ
V = 0V
GB
100n
V = -5V
GB
V = -10V
GB
10n
V = -15V
GB
ID(A)
1.4µ
V = -20V
GB
1n
V = 0V
GB
100p
600.0n
400.0n
V = -5V
GB
V = -10V
GB
10p
200.0n
V = -15V
GB
1p
0.0
V = -20V
GB
100f
-1.0
-0.5
0.0
VGS(V)
0.5
1.0
-1.0
-0.5
First FinFET Transistor (E-beam)
0.0
VGS(V)
0.5
1.0
Electrical Characterization
University of Sao Paulo
WFIN= 100nm, HFIN= 100nm, tox= 4.5nm, tbox = 200nm, L = 3.5µm,
Gate electrode: Si-Poli
VGS = -0,5V
VGS = -0,25V
VGS = 0,0V
VGS = 0,25V
VGS = 0,5V
VGS = 0,75V
VGS = 1,0V
10.0µ
Drain
Gate
Source
ID(A)
8.0µ
6.0µ
4.0µ
VGB=-15V
2.0µ
0.0
0.0
0.2
0.4
0.6
VDS(V)
First FinFET Transistor (E-beam)
0.8
1.0
University of Sao Paulo
Fin Obtained by FIB
Narrowing W
with FIB
University of Sao Paulo
Focused Ion Beam (FIB)
FAPESP PROJECT
University of Sao Paulo
Fin Obtained by FIB
Lithography
+ RIE etch
Narrowing
WFIN
with FIB
University of Sao Paulo
Fin Obtained by FIB
WFin ~ 100 nm
FinFET Transistor (FIB)
University of Sao Paulo
Al TiN SiO2
Al
Si – p
Al
Si
Buried Oxide
Al
Buried Oxide
Si bulk
University of Sao Paulo
First FinFET Transistor (FIB)
WFIN = 50nm, HFIN= 300nm, tox= 10nm, tbox = 400nm, L = 15 µm
Gate electrode: TiN
IDS (A)
1µ
100n
VDS = 0.5 V
VDS = 1.0 V
VDS = 1.5 V
VDS = 2.0 V
10n
0.0
0.5
1.0
VGS (V)
1.5
2.0
University of Sao Paulo
First FinFET Transistor (FIB)
WFIN = 50nm, HFIN= 300nm, tox= 10nm, tbox = 400nm, L = 15 µm
Gate electrode: TiN
VGS = 2 V
3.0µ
IDS (A)
2.0µ
1.0µ
0.0
0
1
VDS (V) 2
3
VGS = 0 V
First FinFET (3D) Transistors
University of Sao Paulo
Drain
Gate
Source
USP (E-Beam)
UNICAMP (FIB)
University of Sao Paulo
EXPECTED RESULTS (OBTAINED)
• Publication of at least 16 journal papers
Real: 2009: 4; 2010: 9; 2011: 16; 2012: 14 (total = 43)
• Publication of at least 64 full paper in a Conference proceedings
Real: 2009: 27; 2010: 34; 2011: 34; 2012: 46 (total = 141)
• Formation of at least 4 Ph.D students.
Real: 2009: 1; 2010: 3; 2011: 1; 2012: 2 (total= 7)
•Formation of at least 8 Master students
Real: 2009: 6; 2010: 3; 2011: 3; 2012: 0 (total = 12)
University of Sao Paulo
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
João Antonio Martino (LSI/USP)
Sebastião Gomes dos Santos Filho (LSI/USP)
José Alexandre Diniz (CCS/UNICAMP)
Marcelo Antonio Pavanello (FEI)
Antonio Carlos Seabra (LSI/USP)
Victor Sonnenberg (LSI/USP)
Paula G. D. Agopian (LSI/USP/FEI)
Milene Galeti (LSI/USP)
Michele Rodrigues (LSI/USP)
Ricardo Rangel (LSI/USP)
Mariana Pojar (LSI/USP) – Pos-Doc
Ioshiaki Doi (CCS/UNICAMP)
Stanislav Moshkalev (CCS/UNICAMP)
Renato Giacomini (FEI)
Michelly de Souza (FEI) – Pos-Doc
Rodrigo Doria (FEI) – Pos-Doc
University of Sao Paulo
University of Sao Paulo
Acknowledgements