Atributos de sinais
sinal‘last_value
sinal‘event
-- o valor do sinal antes do último evento nele
-- true no case de ocorrência de um evento no sinal,
false caso contrário
signal clk : std_logic;
signal y1, y2 : std_logic;
y2 <= clk'last_value;
if (clk'event and clk = '1') then
y <= x;
end if;
Atribuição concorrente de sinais
entity mux4_1 is
Port ( x, y, z, w : in std_logic;
o : out std_logic;
sel : in std_logic_vector(1 downto 0));
end mux4_1;
architecture Behavioral of mux4_1 is
begin
mux: process (sel) is
begin
if (sel = "00") then
o <= x;
elsif (sel = "01") then
o <= y;
elsif (sel = "10") then
o <= z;
else
o <= w;
end if;
end process mux;
end Behavioral;
atribuição
condicional
architecture Behavioral of mux is
begin
o <= x when sel = "00" else
y when sel = "01" else
z when sel = "10" else
w when sel = "11";
end Behavioral;
Atribuição concorrente de sinais
entity mux_case is
Port ( x, y, z, w : in std_logic;
o : out std_logic;
sel : in std_logic_vector(1 downto 0));
end mux_case;
architecture Behavioral of mux_case is
begin
mux: process (sel) is
begin
case sel is
when "00" =>
when "01" =>
when "10" =>
when others =>
end case;
end process mux;
end Behavioral;
o <= x;
o <= y;
o <= z;
o <= w;
atribuição
selectiva
architecture Behavioral of mux is
begin
with sel select
o <= x when "00",
y when "01",
z when "10",
w when others;
end Behavioral;
Atribuição concorrente e agregados
entity full_adder is
Port ( a : in std_logic;
b : in std_logic;
cin : in std_logic;
s : out std_logic;
cout : out std_logic);
end full_adder;
um somador
completo de 1 bit
architecture Behavioral of full_adder is
begin
with std_logic_vector'(a, b, cin) select
(cout, s) <= std_logic_vector'("00") when "000",
std_logic_vector'("01") when "001",
std_logic_vector'("01") when "010",
std_logic_vector'("10") when "011",
std_logic_vector'("01") when "100",
std_logic_vector'("10") when "101",
std_logic_vector'("10") when "110",
std_logic_vector'("11") when others;
end Behavioral;
architecture Behavioral2 of entidade is
signal a, b, c : std_logic;
begin
or2_1: process (x(1), x(2)) is
begin
a <= x(1) or x(2);
end process or2_1;
inv: process (x(3)) is
begin
b <= not x(3);
end process inv;
or2_2: process (b, x(2)) is
begin
c <= b or x(2);
end process or2_2;
and2_1: process (a, c) is
begin
y <= a and c;
end process and2_1;
end Behavioral2;
y  ( x1  x2 )  ( x2  x3 )
x1
x2
x3
a
c
b
y
entity entidade is
Port ( x : in std_logic_vector(3 downto 1);
y : out std_logic);
end entidade;
architecture Behavioral1 of entidade is
begin
y <= (x(1) or x(2)) and (x(2) or not x(3));
end Behavioral1;
entity and2 is
Port ( x : in std_logic;
y : in std_logic;
z : out std_logic);
end and2;
architecture structural of entidade is
signal a, b, c : std_logic;
begin
architecture b of and2 is
begin
z <= x and y; end b; or2_1: entity work.or2(b)
port map (x => x(1), y => x(2), z => a);
entity or2 is
Port ( x : in std_logic;
y : in std_logic;
z : out std_logic);
end or2;
architecture b of or2 is
begin
z <= x or y; end b;
entity inv is
Port ( i : in std_logic;
o : out std_logic);
end inv;
architecture b of inv is
begin
o <= not i; end b;
inv: entity work.inv(b)
port map (i => x(3), o => b);
or2_2: entity work.or2(b)
port map (x => b, y => x(2), z => c);
and2_1: entity work.and2(b)
port map (x => a, y => c, z => y);
end structural;
Descrição parametrizável
entity gen_mux is
Port ( vector : in std_logic_vector;
sel : in std_logic_vector;
o : out std_logic);
end gen_mux;
architecture beh of gen_mux is
begin
o <= vector(conv_integer(sel));
end beh;
entity muxes is
Port ( vector1 : in std_logic_vector (3 downto 0);
vector2 : in std_logic_vector (7 downto 0);
sel1 : in std_logic_vector (1 downto 0);
sel2 : in std_logic_vector (2 downto 0);
o1, o2 : out std_logic);
end muxes ;
architecture structural of muxes is
begin
en1: entity work.gen_mux(beh)
port map( vector => vector1, sel => sel1,
o => o1);
en2: entity work.gen_mux(Behavioral)
port map( vector => vector2, sel => sel2,
o => o2);
end structural;
entity gen_mux is
Generic
generic ( n : natural := 7; k : natural := 2);
Port ( vector : in std_logic_vector (n downto 0);
sel : in std_logic_vector (k downto 0);
o : out std_logic);
entity muxes is
end gen_mux;
Port ( vector1 : in std_logic_vector (3 downto 0);
vector2 : in std_logic_vector (7 downto 0);
architecture beh of gen_mux is
sel1 : in std_logic_vector (1 downto 0);
begin
sel2 : in std_logic_vector (2 downto 0);
o <= vector(conv_integer(sel));
o1, o2 : out std_logic);
end bef;
end muxes;
architecture structural of muxes is
begin
en1: entity work.gen_mux(beh)
generic map (n => vector1'high, k => sel1'high)
port map( vector => vector1, sel => sel1, o => o1);
en2: entity work.gen_mux(bef)
generic map (n => vector2'high, k => sel2'high)
port map( vector => vector2, sel => sel2, o => o2);
end structural;
entity edge_trig_Dff is
Port ( clk : in std_logic;
clr : in std_logic;
d : in std_logic;
q : out std_logic);
end edge_trig_Dff;
entity reg4 is
Port ( clk, clr : in std_logic;
d : in std_logic_vector(3 downto 0);
q : out std_logic_vector(3 downto 0));
end reg4;
architecture estrutural of reg4 is
architecture simple of edge_trig_Dff is
begin
q <= '0' when clr = '1' else
d when rising_edge(clk);
end simple;
instanciação directa
de entidades
begin
bit0: entity work.edge_trig_Dff (simple)
port map (clk, clr, d(0), q(0));
bit1: entity work. edge_trig_Dff (simple)
port map (clk, clr, d(1), q(1));
bit2: entity work. edge_trig_Dff (simple)
port map (clk, clr, d(2), q(2));
bit3: entity work. edge_trig_Dff (simple)
port map (clk, clr, d(3), q(3));
end estrutural;
architecture struct of reg4 is
component edge_trig_Dff is
Port ( clk : in std_logic;
clr : in std_logic;
d : in std_logic;
q : out std_logic);
end component edge_trig_Dff;
declaração
do componente
begin
bit0: component edge_trig_Dff
port map (clk => clk, clr => clr, d => d(0), q => q(0));
bit1: component edge_trig_Dff
port map (clk => clk, clr => clr, d => d(1), q => q(1));
bit2: component edge_trig_Dff
port map (clk => clk, clr => clr, d => d(2), q => q(2));
bit3: component edge_trig_Dff
port map (clk => clk, clr => clr, d => d(3), q => q(3));
end struct;
instanciação
do componente
architecture struct of reg4 is
component DFF is
Port ( clk : in std_logic;
clr : in std_logic;
d : in std_logic;
q : out std_logic);
end component DFF;
for all : DFF
use entity work.edge_trig_Dff(simple);
begin
bit0: component DFF
port map (clk => clk, clr => clr, d => d(0), q => q(0));
bit1: component DFF
port map (clk => clk, clr => clr, d => d(1), q => q(1));
bit2: component DFF
port map (clk => clk, clr => clr, d => d(2), q => q(2));
bit3: component DFF
port map (clk => clk, clr => clr, d => d(3), q => q(3));
end struct;
especificação da
configuração das
instâncias do
componente
Configurações normalmente não são suportadas pelas ferramentas de síntese.
Caso não exista nenhuma configuração explícita, vai ocorrer a ligação por defeito
(default binding): para cada instância de cada componente será seleccionada uma
entidade cujos nome, portas, etc. coincidam com a declaração da componente. Se a
entidade tiver mais que uma arquitectura, será seleccionada aquela que foi analisada
o mais recentemente.
component edge_trig_Dff is
Port ( clk : in std_logic;
clr : in std_logic;
d : in std_logic;
q : out std_logic);
end component edge_trig_Dff;
será utilizada
esta arquitectura
architecture simple of edge_trig_Dff is
begin
q <= '0' when clr = '1' else
d when rising_edge(clk);
end simple;
architecture simple2 of edge_trig_Dff is
begin
q <= '0' when clr = '1' else
(not d) when rising_edge(clk);
end simple2;
architecture simple3 of edge_trig_Dff is
begin
q <= '0' when clr = '1' else
'1' when rising_edge(clk);
end simple3;
entity top is
Port ( clk, rst : in std_logic;
ext_rw, cs_lcd, csn_lcd, ext_a : out std_logic;
ext_d : out std_logic_vector(7 downto 0));
end top;
architecture struct of top is
component BUFGP
port (I: in std_logic; O: out std_logic);
end component BUFGP;
component reg4 is
Port ( clk, clr : in std_logic;
d : in std_logic_vector(3 downto 0);
q : out std_logic_vector(3 downto 0));
end component reg4;
component lcd_reg
port (
clk48, rst : in std_logic;
ext_a, ext_rw, cs_lcd, csn_lcd : out std_logic;
ext_d : out std_logic_vector(7 downto 0);
reg : in std_logic_vector(3 downto 0)
);
end component lcd_reg;
signal clk48, nrst : std_logic;
signal reg_data : std_logic_vector (3 downto 0);
IBUFG + BUFG
entity top is
Port ( clk, rst : in std_logic;
ext_rw, cs_lcd, csn_lcd, ext_a : out std_logic;
ext_d : out std_logic_vector(7 downto 0));
end top;
begin
nrst <= not rst;
clock_buffer : BUFGP
port map (I => clk, O => clk48);
registo : reg4
port map (clk => clk48, clr => nrst, d => "0100", q => reg_data);
LCD : lcd_reg
port map (clk48 => clk48, rst => rst, ext_a => ext_a, ext_d => ext_d,
ext_rw => ext_rw, cs_lcd => cs_lcd, csn_lcd => csn_lcd, reg => reg_data);
end struct;
Instanciação de primitivas
É possível instanciar componentes específicos da arquitectura sem haver
necessidade de especificar a sua definição. Estes componentes são referenciados
por primitivas no Libraries Guide:
Geração estrutural
entity gen_reg is
generic (w : natural);
Port ( clk, clr : in std_logic;
d : in std_logic_vector (w downto 0);
q : out std_logic_vector(w downto 0));
end gen_reg;
architecture struct of gen_reg is
component edge_trig_Dff is
Port ( clk, clr, d : in std_logic;
q : out std_logic);
end component edge_trig_Dff;
begin
component gen_reg is
generic (w : natural);
Port ( clk, clr : in std_logic;
d : in std_logic_vector(w downto 0);
q : out std_logic_vector(w downto 0));
end component gen_reg;
registo : gen_reg
generic map (w => reg_data'high)
port map (clk => clk48, clr => nrst,
d => "0100", q => reg_data);
gen_reg: for i in 0 to w generate
bits: component edge_trig_Dff
port map (clk => clk, clr => clr, d => d(i), q => q(i));
end generate gen_reg;
end struct;
É também possível utilizar comando generate para descrever modelos
comportamentais.
entity proc_gen is
port ( clk : in std_logic;
vector : in std_logic_vector(1 to 3);
result : out std_logic_vector(1 to 3));
end proc_gen;
1 1 0  v1  r1 
0 1 1   v   r 

  2  2
1 0 1  v 3  r3 
architecture Behavioral of proc_gen is
type matrix is array (1 to 3, 1 to 3) of std_logic;
constant transf_matrix : matrix := ( 1 => ('1', '1', '0'), 2 => ('0', '1', '1'),
3 => ('1', '0', '1') );
begin
transformation: for i in 1 to 3 generate
process (clk) is
begin
result(i) <= (transf_matrix(i,1) and vector(1)) or
(transf_matrix(i,2) and vector(2)) or
(transf_matrix(i,3) and vector(3));
end process;
end generate transformation;
end Behavioral;
Geração condicional
entity half_add is
port ( a, b : in std_logic;
sum, cout : out std_logic);
end half_add;
entity full_add is
port ( a, b, cin : in std_logic;
sum, cout : out std_logic);
end full_add;
architecture descr of half_add is
architecture descr of full_add is
begin
sum <= a xor b;
cout <= a and b;
end descr;
begin
sum <= a xor b xor cin;
cout <= (a and b) or (a and cin) or (b and cin);
end descr;
Construir um somador genérico que não tem a entrada de carry
(ripple-carry adder with no carry-in)
entity gen_add is
generic (w : natural);
port ( a, b : in std_logic_vector(w downto 0);
r : out std_logic_vector(w downto 0);
cout : out std_logic);
end gen_add;
architecture struct of gen_add is
component full_add
port (a, b, cin : in std_logic;
sum, cout : out std_logic);
end component;
component half_add
port (a, b : in std_logic;
sum, cout : out std_logic);
end component;
signal carry : std_logic_vector(w downto 0);
.....
begin
gen_som: for i in 0 to w generate
lower_bit: if i = 0 generate
u0: half_add
port map (a => a(i), b => b(i), sum => r(i), cout => carry(i));
end generate lower_bit;
upper_bits: if i > 0 generate
ux: full_add
port map (a => a(i), b => b(i), cin => carry(i - 1),
sum => r(i), cout => carry(i));
end generate upper_bits;
end generate gen_som;
cout <= carry(w);
end struct;
somador : gen_add
generic map (w => reg_data'high)
port map (a => "0100", b => "0011", r => reg_data, cout => open);
Estruturas recursivas
Determinação de paridade de um vector.
d(0)
d(1)
d(0)
l
z
z
d(1)
d(2)
r
d(3)
d(0)
d(1)
l
d(2)
r
d(3)
l
z
d(4)
d(5)
l
d(6)
r
d(7)
r
...
entity rec is
architecture recursive of rec is
generic (w : natural := 7);
signal l, r : std_logic;
port ( d : in std_logic_vector begin
(w downto 0);
z : out std_logic);
simple_tree : if w = 1 generate
end rec;
begin
z <= d(0) xor d(1);
end generate simple_tree;
d(0)
d(1)
l
d(2)
r
d(3)
comp_tree : if w > 1 generate
begin
l
z
d(4)
d(5)
l
d(6)
r
r
left : entity work.rec(recursive)
generic map ((w-1)/2)
port map (d => d((w-1)/2 downto 0), z => l);
d(7)
d(0)
d(1)
l
d(1)
l
d(2)
r
z
d(2)
z
r
d(3)
d(0)
d(1)
right: entity work.rec(recursive)
generic map ((w-1)/2)
port map (d => d(w downto (w-1)/2 + 1), z => r);
d(0)
d(3)
z
d(0)
d(1)
d(0)
z
d(1)
z
d(0)
d(1)
z
z <= l xor r;
end generate comp_tree;
end recursive;