Chapter Six Pipelining Controle Mario Côrtes - MO401 - IC/Unicamp- 2004s2 1998 Morgan Kaufmann Publishers Ch6b-1 Pipeline Control PCSrc 0 M u x 1 IF/ID ID/EX EX/MEM MEM/WB Add dd Add reA sult 4 Shift left2 PC Address Instruction memory Instruction RegWrite Read register 1 MemWrite Read data1 Read register 2 Registers Read Write data2 register Write data Instruction [15–0] 16 Instruction [20–16] Instruction [15–11] Branch Sign 32 extend ALUSrc 0 M u x 1 6 0 M u x 1 Zero Zero ALU ALU result MemtoReg Address Data memory Write data ALU control Read data 1 M u x 0 MemRead ALUOp RegDst • campo function para controle da ALU (EX) • sinais de controle: os mesmos do capítulo 5, ciclo único • PC e registradores de pipeline escritos em todos ciclos: não é necessário controle Mario Côrtes - MO401 - IC/Unicamp- 2004s2 1998 Morgan Kaufmann Publishers Ch6b-2 Pipeline control • We have 5 stages. What needs to be controlled in each stage? – Instruction Fetch and PC Increment – Instruction Decode / Register Fetch – Execution – Memory Stage – Write Back • How would control be handled in an automobile plant? – a fancy control center telling everyone what to do? – should we use a finite state machine? Mario Côrtes - MO401 - IC/Unicamp- 2004s2 1998 Morgan Kaufmann Publishers Ch6b-3 Pipeline Control • Pass control signals along just like the data Instruction R-format lw sw beq Execution/Address Calculation Memory access stage stage control lines control lines Reg ALU ALU ALU Mem Mem Dst Op1 Op0 Src Branch Read Write 1 1 0 0 0 0 0 0 0 0 1 0 1 0 X 0 0 1 0 0 1 X 0 1 0 1 0 0 Write-back stage control lines Reg Mem to write Reg 1 0 1 1 0 X 0 X WB Instruction Control IF/ID Mario Côrtes - MO401 - IC/Unicamp- 2004s2 M WB EX M WB ID/EX EX/MEM MEM/WB 1998 Morgan Kaufmann Publishers Ch6b-4 Datapath with Control PCSrc ID/EX 0 M u x 1 Control IF/ID WB EX/MEM M WB MEM/WB EX M WB Add ALUSrc Read register 1 Read data 1 Read register 2 Registers Read Write data 2 register Write data 0 M u x 1 Zero ALU ALU result MemtoReg Instruction memory Branch Shift left 2 MemWrite Address Instruction PC Add Add result RegWrite 4 Address Data memory Read data Write data Instruction 16 [15–0] Instruction [20–16] Instruction [15–11] Mario Côrtes - MO401 - IC/Unicamp- 2004s2 Sign extend 32 6 ALU control 1 M u x 0 MemRead 0 ALUOp M u x 1 RegDst 1998 Morgan Kaufmann Publishers Ch6b-5 Exemplo (pag. 471) IF : lw $ 1 0 , 2 0 ($ 1 ) 0 M u x 1 ID : b e fo re < 1 > E X : b e fo re < 2 > IF/ID ID/EX WB 00 00 Control 000 0000 M M E M : b e fo re < 3 > W B : b e fo re < 4 > EX/MEM 000 WB 0 EX 00 0 MEM/WB 00 0 M 0 0 0 WB 0 Add Instruction memory Read register1 Read data1 Read register2 Registers Read Write data2 register Write data Instruction [15–0] Sign extend IF : s u b $ 1 1 , $ 2 , $ 3 0 M u x 1 Address Data memory Read data 1 M u x 0 Write data ALU control Instruction [20–16] MemRead 0 ALUOp M u x 1 RegDst Instruction [15–11] C lo c k 1 Zero ALU ALU result ID : lw $ 1 0 , 2 0 ($ 1 ) E X : b e fo re < 1 > IF/ID ID/EX WB 00 11 lw Control 010 0001 M E M : b e fo re < 2 > W B : b e fo re < 3 > EX/MEM M 000 0 EX 00 0 MEM/WB WB 00 0 M 0 0 0 WB 0 Add PC Add Add result Address Instruction memory 1 X Read register1 Read $1 data1 Read register2 Registers Read $X Write data2 register Write data Instruction 20 [15–0] C lo c k 2 Sign extend 20 Instruction 10 [20–16] 10 Instruction [15–11] X X Branch Shift left2 ALUSrc 0 M u x 1 Zero ALU ALU result MemtoReg 4 MemWrite 20($1) $2, $3 $4, $5 $6, $7 $8, $9 0 M u x 1 RegWrite $10, $11, $12, $13, $14, Instruction lw sub and or add ALUSrc MemtoReg Address Branch Shift left2 MemWrite Instruction PC Add Add result RegWrite 4 Address Data memory Read data Write data ALU control 0 ALUOp M u x 1 RegDst MemRead 1 M u x 0 Exemplo (pag. 471) IF : a n d $ 1 2 , $ 4 , $ 5 0 M u x 1 ID : s u b $ 1 1 , $ 2 , $ 3 E X : lw $ 1 0 , . . . IF/ID ID/EX WB 11 10 sub Control 000 1100 M E M : b e fo re < 1 > W B : b e fo re < 2 > EX/MEM M 010 0 EX 00 1 MEM/WB WB 00 0 M 0 0 0 WB 0 Add Instruction memory C lo c k 3 IF : o r $ 1 3 , $ 6 , $ 7 0 M u x 1 Read register 1 Read $2 data1 Read register 2 Registers Read $3 Write data2 register Write data X Instruction [15–0] X $1 0 M u x 1 X 20 Instruction [20–16] X 10 Instruction 11 [15–11] 11 Sign extend ID : a n d $ 1 2 , $ 2 , $ 3 Control 000 1100 Read data 1 M u x 0 Write data ALU control MemRead 0 ALUOp M u x 1 RegDst ID/EX WB 10 10 Address Data memory E X : sub $1 1, . . . IF/ID and Zero ALU ALU result M E M : lw $ 1 0 , . . . EX/MEM M 000 1 EX 10 0 W B : b e fo re < 1 > MEM/WB WB 11 0 M 1 0 0 WB 0 Add PC Add Addresult Address Instruction memory 4 5 Read register 1 Read $4 data1 Read register 2 Registers Read $5 Write data2 register X Instruction [15–0] X Instruction [20–16] X Instruction 12 [15–11] 12 Sign extend ALUSrc $2 $3 Write data C lo c k 4 Branch Shift left2 X 0 M u x 1 Zero ALU ALU result Address Data memory Read data Write data ALU control 11 MemtoReg 4 MemWrite 20($1) $2, $3 $4, $5 $6, $7 $8, $9 3 RegWrite $10, $11, $12, $13, $14, Instruction lw sub and or add 2 ALUSrc MemtoReg Address Branch Shift left2 MemWrite Instruction PC Add Addresult RegWrite 4 0 ALUOp M u x 1 RegDst MemRead 10 1 M u x 0 Exemplo (pag. 471) IF : a d d $ 1 4 , $ 8 , $ 9 0 M u x 1 ID : o r $ 1 3 , $ 6 , $ 7 E X : and $12, . . . IF/ID ID/EX WB 10 10 or Control 000 1100 M M E M : sub $1 1, . . . EX/MEM 000 WB 1 EX 10 0 W B : lw $ 1 0 , . . . MEM/WB 10 0 M 0 0 1 WB 1 Add Instruction memory C lo c k 5 IF : a fte r< 1 > X Instruction [15–0] X Instruction [20–16] X Instruction 13 [15–11] 13 Zero ALU ALU result 000 1100 Address Data memory ALU control 12 M Read data 1 M u x 0 Write data MemRead 0 ALUOp M u x 1 RegDst ID/EX 10 WB 10 Control 0 M u x 1 EX : or $13 , . . . IF/ID add $5 X Sign extend ID : a d d $ 1 4 , $ 8 , $ 9 0 M u x 1 $4 11 10 M E M : an d $12, . . . EX/MEM 000 WB 1 EX 10 0 W B : su b $ 1 1 , . . . MEM/WB 10 0 M 0 0 1 WB 0 Add PC Add Add result Address Instruction memory 8 9 11 Read register1 Read $8 data1 Read register2 Registers Read $9 Write data2 register X Instruction [15–0] X Instruction [20–16] X Instruction 14 [15–11] 14 Sign extend ALUSrc $6 $7 Write data C lo c k 6 Branch Shift left 2 X 0 M u x 1 Zero ALU ALU result Address Data memory Read data 1 M u x 0 Write data ALU control 13 MemtoReg 4 MemWrite 20($1) $2, $3 $4, $5 $6, $7 $8, $9 Read register1 Read $6 data1 Read register2 Registers Read $7 Write data2 register Write data RegWrite $10, $11, $12, $13, $14, 7 10 Instruction lw sub and or add 6 ALUSrc MemtoReg Address Branch Shift left 2 MemWrite Instruction PC Add Add result RegWrite 4 0 ALUOp M u x 1 RegDst MemRead 12 11 Exemplo (pag. 471) IF : a fte r< 2 > ID : a fte r< 1 > 0 M u x 1 E X: add $ 14, . . . IF/ID 00 Control 000 0000 ID/EX WB 10 M EM : or $13, . . . EX/MEM M 000 1 EX 10 0 W B: and $1 2, . . . MEM/WB WB 10 0 M 0 0 1 WB 0 Add Instruction memory $8 $9 Sign extend IF : a fte r< 3 > Instruction [15–11] 14 ID : a fte r< 2 > 0 M u x 1 Zero ALU ALU result Address Data memory 00 Control 000 0000 1 M u x 0 MemRead 0 ALUOp M u x 1 RegDst E X : a fte r < 1 > IF/ID Read data Write data ALU control Instruction [20–16] C lo c k 7 0 M u x 1 13 12 M EM : add $14, . . . ID/EX WB 00 EX/MEM M 000 0 EX 00 0 W B: or $13, . . . MEM/WB WB 10 0 M 0 0 1 WB 0 Add PC Add Add result Address Instruction memory 13 Read register 1 Read data1 Read register 2 Registers Read Write data2 register Write data Instruction [15–0] Instruction [20–16] C lo c k 8 Instruction [15–11] Branch Shift left2 Sign extend ALUSrc 0 M u x 1 Zero ALU ALU result MemtoReg 4 MemWrite 20($1) $2, $3 $4, $5 $6, $7 $8, $9 RegWrite $10, $11, $12, $13, $14, Instruction [15–0] Instruction lw sub and or add 12 Read register 1 Read data1 Read register 2 Registers Read Write data2 register Write data ALUSrc MemtoReg Address Branch Shift left2 MemWrite Instruction PC Add Add result RegWrite 4 Address Data memory Read data 1 M u x 0 Write data ALU control 0 ALUOp M u x 1 RegDst MemRead 14 13