Scan design
techniques
J. M. Martins Ferreira
FEUP / DEEC - Rua Dr. Roberto Frias
4200-537 Porto - PORTUGAL
Tel. 351 225 081 748 / Fax: 351 225 081 443
([email protected] / http://www.fe.up.pt/~jmf)
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
1
Objectives
• To introduce the basic concepts in design
for test
• To prepare the introduction of the standard
boundary-scan test architecture
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
2
Outline
• Testability and test generation in sequential
circuits
• Testability improvement via ad hoc
solutions
• Structured approaches to design for
testability
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
3
Test generation for
sequential circuits
Combinational block
1
X s@0
(1/0)
U?A
3
2
7408
1
U?A
3
2
0
X
1
0
U?A
Circuit
primary
output
F=1/0
7432
3
2
Next
state
output
Y
7408
VCC_BAR
6
U?A
7474
Q
CL
CLK
5
Q
PR
D
3
2
4
VCC_BAR
U?A
7474
1
6
Q
CL
CLK
5
Q
PR
D
3
2
4
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
1
1
1
• Direct application
of the D-algorithm
leads to the
combinational
circuit inputs and
outputs, not
necessarily to
primary inputs or
outputs
Next
state
output
A
VCC_BAR
CLK
4
Test generation - step 1
This is the initial circuit state,
Combinational block
A=1
0
0
1
Next
state
output
X s@0
(0/0)
U? A
3
2
7408
1
U? A
3
2
1
1
1
1
U? A
where we assume that both flip-
Circuit
primary
output
flops are at 0. Fault detection is
F=1
7432
3
2
Next
state
output
7408
not possible because neither fault
activation nor fault propagation
VCC_ BAR
Q
CL
CL K
5
Q
PR
0
6
take place.
U? A
7474
1
1
D
3
CLK
2
4
VCC_ BAR
6
Q
CL K
Q
PR
5
A
CL
0
U? A
7474
1
1
D
3
2
4
VCC_ BAR
CLK
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
F
5
Test generation - step 2
The first clock cycle is applied with
Combinational block
A=1
0
1
1
Next
state
output
X s@0
(0/0)
U? A
3
2
7408
1
U? A
3
2
1
0
1
0
U? A
A=1, leading the circuit to a new state
Circuit
primary
output
which is still not capable of activating
F=0
7432
3
2
Next
state
output
7408
the fault. Fault propagation would
however be possible, since the other
VCC_ BAR
Q
CL
CL K
5
Q
PR
0
6
OR input is now at 0.
U? A
7474
1
1
D
3
2
1
4
CLK
VCC_ BAR
6
Q
CL
CL K
5
Q
PR
1
U? A
7474
1
0
D
A
3
2
4
VCC_ BAR
CLK
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
F
6
Test generation - step 3
The second clock cycle is applied with
Combinational block
A=1
1
1
1
Next
state
output
X s@0
(1/0)
U?A
3
2
7408
1
U?A
3
2
0
0
1
0
U?A
A=1 and guarantees fault detection,
Circuit
primary
output
because the circuit is now brought to a
F=1/0
7432
3
2
Next
state
output
7408
state where fault activation and fault
propagation are simultaneously
VCC_BAR
Q
CL
CLK
5
Q
PR
1
6
possible.
U?A
7474
1
0
D
3
2
1
4
CLK
VCC_BAR
6
Q
CLK
Q
PR
5
A
CL
1
U?A
7474
1
0
D
3
2
fault-free
4
VCC_BAR
CLK
F
X s@0
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
7
The general case is however
much more complex...
• The D-algorithm does not necessarily lead
to circuit primary inputs and outputs
• Knowledge of the state transition diagram
is required
• It may happen that the fault affects the
state transition diagram, in which case the
required sequence at the circuit primary
inputs becomes even harder to find
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
8
The case of Y s@0
Combinational block
1
1
1
X s@0
(1/0)
U?A
3
2
7408
1
U?A
3
2
0
X
1
0
U?A
Circuit
primary
output
F=1/0
7432
3
2
Next
state
output
Y
7408
VCC_BAR
U?A
7474
1
6
Q
CL
CLK
5
Q
PR
D
3
2
4
VCC_BAR
U?A
7474
1
• Test vector
generation for a
fault that affects
the state transition
diagram will help
us to understand
the problem
Next
state
output
A
Q
CL
6
CLK
Q
PR
5
D
3
2
4
VCC_BAR
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
CLK
9
The case of Y s@0 (cont.)
• Modification in the state transition diagram:
Combinational block
Next
state
output
A
0
Q1,Q0=00
0
0,1
0
Q1,Q0=00
1
1
1
X s@0
(1/0)
U?A
3
2
7408
1
0
0,1
01
1
1
1
01
3
2
0
X
1
0
U?A
Circuit
primary
output
F=1/0
7432
3
2
Next
state
output
Y
7408
0
U?A
1
VCC_BAR
2
3
2
VCC_BAR
6
Q0
Q
U?A
7474
CLK
5
Q
PR
D
3
2
4
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
D
3
CL
11
Q
1
11
1
Q1
CLK
5
4
3
States 1 and 3
(Q0=1) are no
longer accessible
Q
PR
0
10
6
CL
10
U?A
7474
1
2
1
VCC_BAR
CLK
10
Ad hoc testability
improvements
• Design rules or amendments to avoid or
minimise test vector generation problems
• Major drawbacks:
– Not always reusable
– Testability depends largely on the type of
circuit
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
11
Some ad hoc testability
rules
• Split counters to avoid high numbers of
clock cycles until the required output
combination is achieved
• Include reset and preset lines
(synchronous or asynchronous)
• Partition large circuits and add extra inputs
and outputs for direct controllability and
observability of internal nodes
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
12
Structured Design for
Testability (DfT)
• Structured DfT methodologies enable a
simple way to drive the circuit to any given
state in a fixed (and short) number of clock
cycles
• Does structured DfT have drawbacks?
– Design rules (design styles) have to accepted
– Additional silicon area, more pins and higher
propagation delays… but is this an additional
cost?
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
13
The scan design principle
SCAN OUT
6
Q
CL
CLK
5
Q
D
3
2
2:1 mux
0
4
Present
state
PR
Next
state
1
Test Mode
VCC_BAR
VCC_BAR
U?A
7474
1
6
Q
CL
CLK
5
Q
D
3
2
2:1 mux
0
4
Present
state
PR
1
Test Mode
VCC_BAR
Next
state
VCC_BAR
U?A
7474
1
6
Q
CL
CLK
5
Q
D
4
Present
state
PR
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
U?A
7474
1
• The scan design
principle
consists of
inserting a 2:1
multiplexer
between the
input of every D
flip-flop and its
driving logic
VCC_BAR
3
2
2:1 mux
0
Next
state
1
VCC_BAR
Test Mode
TEST MODE
SCAN IN
CLOCK
14
Scan design advantages (1)
• Problem: Part of the combinational circuit
inputs are not directly controllable, since
they come from the D-FF outputs (these
nodes define the present state of the circuit)
• Solution: Scan flip-flops enable direct
controllability of the D-FF outputs through
a simple procedure with a fixed number of
clock cycles
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
15
Better controllability
through scan design (1)
SCAN OUT
1
VCC_BAR
U?A
7 47 4
1
Q
CL
6
CLK
5
Q
D
3
2
2:1 mux
0
0
4
Present
state
PR
1
Next
state
1
Test Mode
VCC_BAR
VCC_BAR
U?A
7 47 4
1
Q
CL
6
CLK
5
Q
D
3
2
2:1 mux
0
0
4
Present
state
PR
0
1
Test Mode
VCC_BAR
Next
state
Since the Test Mode control signal is at 0,
VCC_BAR
U?A
7 47 4
1
Q
CL
6
CLK
5
D
each clock cycle will transfer to the D-FF
3
2
2:1 mux
1
0
4
Present
state
Q
PR
0
Example
Take the circuit to
state 110, starting
from state 100
(intrusive)
outputs the values present at the next
Next
state
1
VCC_BAR
Test Mode
0
1
TEST MODE
SCAN IN
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
state nodes.
CLOCK
16
Better controllability
through scan design (2)
SCAN OUT
0
VCC_ BAR
1
U? A
74 74
Q
CL K
Q
D
3
2
2:1 mux
Next
state
1
Test Mode
VCC_ BAR
register. The first clock cycle applied will
?
0
4
Present
state
PR
0
5
and the D-FFs are connected as a shift-
CL
6
The Test Mode control signal is now at 1
shift the D-FFs one bit position “up” and
VCC_ BAR
U? A
74 74
1
Q
CL K
5
Q
PR
0
D
3
2
2:1 mux
Next
state
1
Test Mode
VCC_ BAR
input to the output of the first D-FF in the
?
0
4
Present
state
transfer the value present at the Scan In
CL
6
chain.
The values shown at each node are those
VCC_ BAR
U? A
74 74
1
Q
CL
6
CL K
5
Q
D
following the application of the first clock
3
2
2:1 mux
?
0
4
Present
state
PR
1
cycle with Scan In at 1.
Next
state
1
VCC_ BAR
Test Mode
1
1
TEST MODE
SCAN IN
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
CL OCK
17
Better controllability
through scan design (3)
SCAN OUT
0
VCC_ BAR
1
U? A
74 74
Q
CL K
Q
D
3
2
2:1 mux
Next
state
1
Test Mode
VCC_ BAR
second clock cycle, keeping Scan In at 1.
?
0
4
Present
state
PR
0
5
those following the application of the
CL
6
The values shown at each node are now
Notice that the initial present state
VCC_ BAR
U? A
74 74
1
Q
CL K
5
Q
PR
1
D
3
2
2:1 mux
Next
state
1
Test Mode
VCC_ BAR
simultaneously as the new present state
?
0
4
Present
state
values are being shifted out
CL
6
is being shifted in.
VCC_ BAR
U? A
74 74
1
Q
CL
6
CL K
5
Q
D
3
2
2:1 mux
?
0
4
Present
state
PR
1
Next
state
1
VCC_ BAR
Test Mode
1
1
TEST MODE
SCAN IN
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
CL OCK
18
Better controllability
through scan design (4)
SCAN OUT
1
VCC_ BAR
1
U? A
74 74
Q
CL K
5
Q
PR
1
D
3
2
2:1 mux
Next
state
1
Test Mode
VCC_ BAR
present state is 110 as requested.
?
0
4
Present
state
with the Scan In input set at 0, so the new
CL
6
The last clock cycle has now been applied
Three clock cycles were therefore
VCC_ BAR
U? A
74 74
1
Q
CL K
5
Q
PR
1
D
3
2
2:1 mux
Next
state
1
Test Mode
VCC_ BAR
present state, the general rule being that
?
0
4
Present
state
necessary to take the circuit to its new
CL
6
the number of clock cycles required is
equal to the number of D-FFs.
VCC_ BAR
U? A
74 74
1
Q
CL
6
CL K
5
D
3
2
2:1 mux
?
0
4
Present
state
Q
PR
0
Next
state
1
VCC_ BAR
Test Mode
1
0
TEST MODE
SCAN IN
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
CL OCK
19
Better controllability
through scan design (5)
SCAN OUT
1
VCC_ BAR
1
U? A
74 74
Q
CL K
5
Q
D
3
2
2:1 mux
Next
state
1
Test Mode
VCC_ BAR
has been taken back to 0.
?
0
4
Present
state
PR
1
loaded and the Test Mode control signal
CL
6
The requested present state has been
Each next state node is now connected to
VCC_ BAR
U? A
74 74
1
Q
CL K
5
Q
PR
1
D
3
2
2:1 mux
Next
state
1
Test Mode
VCC_ BAR
by the combinational logic block
?
0
4
Present
state
the respective D-FF input and is defined
CL
6
according to present state 110 and to the
current values at the (external) circuit
VCC_ BAR
U? A
74 74
1
Q
CL
6
CL K
5
Q
D
primary inputs.
3
2
2:1 mux
?
0
4
Present
state
PR
0
Next
state
1
VCC_ BAR
Test Mode
0
X
TEST MODE
SCAN IN
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
CL OCK
20
Scan design advantages (2)
• Problem: Part of the combinational circuit
outputs are not directly observable, since
they go to the D-FF inputs (these nodes
define the circuit next state)
• Solution: Scan flip-flops enable direct
observability of the D-FF inputs through a
simple procedure with a fixed number of
clock cycles
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
21
Better observability
through scan design (1)
SCAN OUT
1
VCC_BAR
U?A
7 47 4
1
Q
CL
6
CLK
5
Q
D
3
2
2:1 mux
0
0
4
Present
state
PR
1
Next
state
1
Test Mode
VCC_BAR
VCC_BAR
U?A
7 47 4
1
Q
CL
6
CLK
5
Q
D
3
2
2:1 mux
0
0
4
Present
state
PR
0
1
Test Mode
VCC_BAR
Next
state
The initial circuit conditions are the same
VCC_BAR
CL
Q
CLK
5
Q
D
3
2
2:1 mux
state being 100.
1
0
4
Present
state
PR
0
as in the previous example, the present
U?A
7 47 4
1
6
Example
Observe the next
state (eventually
non-intrusive)
Next
state
1
VCC_BAR
The 2:1 multiplexers have their Test
Test Mode
Mode control signal at 0 and are therefore
0
1
TEST MODE
SCAN IN
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
CLOCK
in “transparent” mode.
22
Better observability
through scan design (2)
SCAN OUT
0
VCC_BAR
1
U?A
7 47 4
Q
CLK
5
Q
PR
0
D
3
2
2:1 mux
Next
state
1
Test Mode
VCC_BAR
cycle. Since the Test Mode control signal
?
0
4
Present
state
following the application of the first clock
CL
6
The values shown at each node are those
was kept at 0, the values transferred to
VCC_BAR
U?A
7 47 4
1
Q
CLK
5
Q
PR
0
D
3
2
2:1 mux
Next
state
1
Test Mode
VCC_BAR
the next state nodes, defined by the
?
0
4
Present
state
the D-FF outputs were those present in
CL
6
(internal) outputs of the combinational
logic block. Notice that the value present
VCC_BAR
U?A
7 47 4
1
Q
CL
6
CLK
5
Q
D
at the Scan Out output is now the first bit
3
2
2:1 mux
?
0
4
Present
state
PR
1
to be shifted out.
Next
state
1
VCC_BAR
Test Mode
0
X
TEST MODE
SCAN IN
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
CLOCK
23
Better observability
through scan design (3)
SCAN OUT
0
VCC_BAR
1
U?A
7 47 4
Q
CLK
5
Q
PR
0
D
3
2
2:1 mux
Next
state
1
Test Mode
VCC_BAR
are those following the application of the
?
0
4
Present
state
to 1 and the values shown at each node
CL
6
The Test Mode control signal was now set
second clock cycle. Since the D-FFs are
VCC_BAR
U?A
7 47 4
1
Q
CLK
5
Q
PR
1
D
3
2
2:1 mux
Next
state
1
Test Mode
VCC_BAR
present state nodes were shifted one bit
?
0
4
Present
state
now connected as a shift-register, the
CL
6
position “up” and the second bit was
shifted out.
VCC_BAR
U?A
7 47 4
1
Q
CL
6
CLK
5
Q
D
3
2
2:1 mux
?
0
4
Present
state
PR
X
Next
state
1
VCC_BAR
Test Mode
1
X
TEST MODE
SCAN IN
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
CLOCK
24
Better observability
through scan design (4)
SCAN OUT
1
VCC_BAR
1
U?A
7 47 4
Q
CLK
5
Q
PR
1
D
3
2
2:1 mux
Next
state
1
Test Mode
VCC_BAR
clock cycle. The last bit (the rightmost bit
?
0
4
Present
state
the application of the third (and last)
CL
6
The values now shown are those following
in the initial 001 next state) was now
VCC_BAR
U?A
7 47 4
1
Q
CLK
5
Q
PR
X
D
3
2
2:1 mux
1
Test Mode
VCC_BAR
Notice that only two clock cycles were
?
0
4
Present
state
shifted out.
CL
6
Next
state
required after the Test Mode control
signal was set to 1, since the first bit is
VCC_BAR
U?A
7 47 4
1
Q
CL
6
CLK
5
D
immediately present at the Scan Out
3
2
2:1 mux
?
0
4
Present
state
Q
PR
X
output.
Next
state
1
VCC_BAR
Test Mode
1
X
TEST MODE
SCAN IN
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
CLOCK
25
Better observability
through scan design (5)
SCAN OUT
1
VCC_BAR
1
U?A
7 47 4
Q
CLK
5
Q
PR
1
D
3
2
2:1 mux
Next
state
1
Test Mode
VCC_BAR
operation mode.
?
0
4
Present
state
brings the circuit back to the normal
CL
6
Setting the Test Mode control signal to 0
The present state was modified as defined
VCC_BAR
U?A
7 47 4
1
Q
CLK
5
Q
PR
X
D
3
2
2:1 mux
Next
state
1
Test Mode
VCC_BAR
state values were modified accordingly.
?
0
4
Present
state
by the values shifted in and the next
CL
6
Notice however that the initial present
state might have been kept…how?
VCC_BAR
U?A
7 47 4
1
Q
CL
6
CLK
5
Q
D
3
2
2:1 mux
?
0
4
Present
state
PR
X
Next
state
1
VCC_BAR
Test Mode
0
X
TEST MODE
SCAN IN
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
CLOCK
26
DfT: Eventually an overhead
• The 2:1 muxs increase the propagation
delay and require additional silicon area
and pins, but will this increase cost?
• How do we quantify the benefits of easier
test vector generation and application?
• Design freedom was traded for higher
testability, but partial scan design might be
a preferred intermediate solution
Leonardo da Vinci ALLEGRO
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
27